公开(公告)号：US20190173439A1

公开(公告)日：2019-06-06

申请号：US16208398

申请日：2018-12-03

Applicant: Qualcomm Incorporated

Inventor： Jeremy DUNWORTH ,  Hyunchul PARK ,  Bon-Hyun KU ,  Vladimir APARIN

IPC: H03F3/21 ,  H03F3/195 ,  H03F3/213 ,  H03F1/56

Abstract: The present disclosure provides an amplifier circuit that includes one or more amplifier stages, each of the one or more amplifier stages including a complementary transistor configuration. The complementary transistor configuration includes an NMOS transistor and a PMOS transistor. The NMOS transistor is electrically coupled in parallel to the PMOS transistor. The amplifier circuit further includes an output amplifier stage electrically coupled to an output of the one or more amplifier stages, the output amplifier stage including a non-complementary transistor configuration including one or more NMOS transistors or PMOS transistors.

公开(公告)号：US20190081399A1

公开(公告)日：2019-03-14

申请号：US15940888

申请日：2018-03-29

Applicant: QUALCOMM Incorporated

Inventor： Bon-Hyun KU ,  Jeremy DUNWORTH

IPC: H01Q5/335 ,  H04B1/44

Abstract: A signal processing circuit reduces die size and power consumption for each antenna element. The signal processing circuit includes a first set of ports, a third port, a first path, a second path and a first transistor. The first path is between a first port of the first set of ports and the third port. The second path is between a second port of the first set of ports and the third port. The first transistor is coupled between the first path and the second path. The first transistor is configured to receive a control signal to control the first transistor to adjust an impedance between the first path and the second path.