公开(公告)号：US10459731B2

公开(公告)日：2019-10-29

申请号：US14803728

申请日：2015-07-20

Applicant: QUALCOMM Incorporated

Inventor： Eric Mahurin ,  Jakub Pawel Golab

IPC: G06F9/302 ,  G06F9/315 ,  G06F15/80 ,  G06F9/38 ,  G06F9/30 ,  G06F15/82

Abstract: A first register has a lane storing first input data and a second register has a lane storing second input data elements. A width of the lane of the second register is equal to a width of the lane of the first register. A single-instruction-multiple-data (SIMD) lane has a lane width equal to the width of the lane of the first register. The SIMD lane is configured to perform a sliding window operation on the first input data elements in the lane of the first register and the second input data elements in the lane of the second register. Performing the sliding window operation includes determining a result based on a first input data element stored in a first position of the first register and a second input data element stored in a second position of the second register. The second position is different from the first position.

公开(公告)号：US11561792B2

公开(公告)日：2023-01-24

申请号：US14732784

申请日：2015-06-08

Applicant: QUALCOMM Incorporated

Inventor： Eric Mahurin ,  Jakub Pawel Golab

IPC: G06F9/30 ,  G06F9/38 ,  G06F1/10

Abstract: A transient load instruction for a processor may include a transient or temporary load instruction that is executed in parallel with a plurality of input operands. The temporary load instruction loads a memory value into a temporary location for use within the instruction packet. According to some examples, a VLIW based microprocessor architecture may include a temporary cache for use in writing/reading a temporary memory value during a single VLIW packet cycle. The temporary cache is different from the normal register bank that does not allow writing and then reading the value just written during the same VLIW packet cycle.

公开(公告)号：US20170024218A1

公开(公告)日：2017-01-26

申请号：US14803728

申请日：2015-07-20

Applicant: QUALCOMM Incorporated

Inventor： Eric Mahurin ,  Jakub Pawel Golab

IPC: G06F9/38 ,  G06F9/30 ,  G06F15/82

Abstract: A first register has a lane storing first input data and a second register has a lane storing second input data elements. A width of the lane of the second register is equal to a width of the lane of the first register. A single-instruction-multiple-data (SIMD) lane has a lane width equal to the width of the lane of the first register. The SIMD lane is configured to perform a sliding window operation on the first input data elements in the lane of the first register and the second input data elements in the lane of the second register. Performing the sliding window operation includes determining a result based on a first input data element stored in a first position of the first register and a second input data element stored in a second position of the second register. The second position is different from the first position.

Abstract translation: 第一寄存器具有存储第一输入数据的通道，第二寄存器具有存储第二输入数据元素的通道。 第二寄存器的通道的宽度等于第一寄存器的通道的宽度。 单指令多数据（SIMD）通道的通道宽度等于第一个寄存器的通道的宽度。 SIMD通道被配置为对第一寄存器的通道中的第一输入数据元素和第二寄存器的通道中的第二输入数据元素执行滑动窗口操作。 执行滑动窗口操作包括基于存储在第一寄存器的第一位置的第一输入数据元素和存储在第二寄存器的第二位置的第二输入数据元素来确定结果。 第二个位置与第一个位置不同。