公开(公告)号：US11361817B2

公开(公告)日：2022-06-14

申请号：US17002082

申请日：2020-08-25

Applicant: QUALCOMM Incorporated

Inventor： Arun Babu Pallerla ,  Changho Jung ,  Sung Son ,  Jason Cheng ,  Yandong Gao ,  Chulmin Jung ,  Venugopal Boynapalli

IPC: G11C16/04 ,  G11C11/4096 ,  G11C11/408 ,  G11C5/02 ,  G11C11/4074 ,  G11C11/4094

Abstract: A bitcell architecture for a pseudo-triple-port memory is provided that includes a a bitcell arranged on a semiconductor substrate, the bitcell defining a bitcell width and a bitcell height and including a first access transistor and a second access transistor. A first metal layer adjacent the semiconductor substrate is patterned to form a pair of local bit lines arranged within the bitcell width. The pair of local bit lines includes a local bit line coupled to a terminal of the first access transistor and includes a complement local bit line coupled to a terminal of the second access transistor.