公开(公告)号：US20240403216A1

公开(公告)日：2024-12-05

申请号：US18325419

申请日：2023-05-30

Applicant: QUALCOMM Incorporated

Inventor： Darshan Kumar Nandanwar ,  Kartik Gunvantbhai Desai

IPC: G06F12/0804 ,  G06F12/1009

Abstract: Optimizing cache energy consumption in processor-based devices is disclosed herein. In some aspects, a processor-based device comprises a way lookup table (WLUT) circuit that is configured to receive an effective address (EA) for a memory access request. The WLUT circuit determines that a tag portion of the EA corresponds to a tag of a WLUT entry among a plurality of WLUT entries. In response, the WLUT circuit transmits a predicted way indicator of the WLUT entry to a cache controller. The cache controller accesses, in a set among a plurality of sets of a cache memory device corresponding to a set portion of the EA, only a predicted tag way among a plurality of tag ways of the cache memory device indicated by the predicted way indicator and only a predicted data way among a plurality of data ways of the cache memory device indicated by the predicted way indicator.

公开(公告)号：US20250087295A1

公开(公告)日：2025-03-13

申请号：US18466110

申请日：2023-09-13

Applicant: QUALCOMM Incorporated

Inventor： Darshan Kumar Nandanwar ,  Kartik Gunvantbhai Desai ,  Raghava Rao M V

IPC: G11C29/00 ,  G11C7/10

Abstract: This disclosure provides systems, methods, and devices for memory systems that support SRAM fault correction. In a first aspect, a method includes receiving, by a memory controller coupled to a memory module through a first channel and configured to store data in and access data stored in the memory module through the first channel from a host device, data to be stored in a memory of the memory module, determining, by the memory controller, a row in the memory at which the data will be stored, determining, by the memory controller based on the row, an address associated with the row, wherein the address indicates one bit location in the row at which data will not be stored, and storing, by the memory controller, the data at the row in accordance with the address, wherein the data is not stored at the one bit location.