公开(公告)号：US11687104B2

公开(公告)日：2023-06-27

申请号：US17213044

申请日：2021-03-25

Applicant: QUALCOMM Incorporated

Inventor： Kuan Chuang Koay ,  Hua Guan ,  Jize Jiang

IPC: G05F1/56 ,  H03F3/16

CPC classification number: G05F1/56 ,  H03F3/16

Abstract: In certain aspects, a system includes an amplifying circuit having an input and an output, wherein the input of the amplifying circuit is coupled to a gate of a pass transistor of a low dropout (LDO) regulator. The system also includes a metal-oxide-semiconductor (MOS) capacitor coupled between the output of the amplifying circuit and the input of the amplifying circuit.

公开(公告)号：US12181903B2

公开(公告)日：2024-12-31

申请号：US18315402

申请日：2023-05-10

Applicant: QUALCOMM Incorporated

Inventor： Kuan Chuang Koay ,  Hua Guan ,  Jize Jiang

IPC: G05F1/56 ,  H03F3/16

Abstract: In certain aspects, a system includes an amplifying circuit having an input and an output, a high-pass filter coupled between a gate of a pass transistor of a low dropout (LDO) regulator and the input of the amplifying circuit, and a metal-oxide-semiconductor (MOS) capacitor coupled between the output of the amplifying circuit and the gate of the pass transistor.

公开(公告)号：US11409313B2

公开(公告)日：2022-08-09

申请号：US17138463

申请日：2020-12-30

Applicant: QUALCOMM Incorporated

Inventor： Jize Jiang ,  Hua Guan ,  Kuan Chuang Koay

IPC: G05F1/56 ,  H04B1/40

Abstract: Aspects of the present disclosure provide a voltage reference architecture. An example circuit generally includes a resistor ladder, a reference current source, and a plurality of multiplexers. The resistor ladder comprises a plurality of resistive elements coupled in series. The reference current source has an output coupled to the resistor ladder. The plurality of multiplexers have inputs coupled to one or more nodes between the plurality of resistive elements and the output of the reference current source, each of the multiplexers having an output selectively coupled to one of the inputs of the multiplexer.

公开(公告)号：US11803204B2

公开(公告)日：2023-10-31

申请号：US17239377

申请日：2021-04-23

Applicant: QUALCOMM Incorporated

Inventor： Xiaodong Meng ,  Fan Yang ,  Yufei Pan ,  Hua Guan ,  Kuan Chuang Koay ,  Jize Jiang

IPC: G05F1/59 ,  G05F1/575 ,  H04B1/40

CPC classification number: G05F1/59 ,  G05F1/575 ,  H04B1/40

Abstract: The disclosure relates to an apparatus including: a first set of one or more field effect transistors (FETs) coupled between a first voltage rail and a load; a second set of one or more FETs coupled between the first voltage rail and the load; a gate voltage control circuit configured to: provide a first set of gate voltages to first and second gates of the first and second sets of one or more FETs in accordance with a first mode of operation, respectively; and provide a second set of gate voltages to the first and second gates of the first and second sets of one or more FETs in accordance with a second mode of operation, respectively; and a voltage droop compensation circuit configured to control an output voltage across the load during a transition from the first mode of operation to the second mode of operation.

公开(公告)号：US11385667B2

公开(公告)日：2022-07-12

申请号：US16724150

申请日：2019-12-20

Applicant: QUALCOMM Incorporated

Inventor： Kuan Chuang Koay ,  Hua Guan ,  YuFei Pan

IPC: G05F1/575 ,  G05F1/59

Abstract: An LDO regulator is provided that includes a bias circuit that generates a bias current having a non-linear relationship to an output current for the LDO regulator. The LDO regulator is also configured to clamp the output current.