公开(公告)号：US20250130801A1

公开(公告)日：2025-04-24

申请号：US18491455

申请日：2023-10-20

Applicant: QUALCOMM Incorporated

Inventor： Shekhar Yeshwant Borkar ,  Nitin Yeshwant Borkar ,  Rishi Khan

IPC: G06F9/30

Abstract: Aspects disclosed in the detailed description include a processing unit (PU) employing micro-operations (micro-ops) random access memory (RAM) as main program memory. The micro-ops RAM comprises row circuits each associated with a micro-op and configured to store control signal parameters and output ports configured to be coupled to a register file and one or more execution units. In contrast to fetching and decoding instructions of an ISA in a conventional PU, the processing unit loads a main program comprising micro-ops into the row circuits of the micro-ops RAM. When executing an individual micro-op of the main program, the processing unit activates a row circuit in the micro-ops RAM to cause its stored control signal parameters to be communicated through the output ports of the micro-ops RAM to the register file and/or the one or more execution units and avoids the need for a decoding stage circuit, advantageously decreasing processing latency.