公开(公告)号：US11061822B2

公开(公告)日：2021-07-13

申请号：US16113141

申请日：2018-08-27

Applicant: QUALCOMM Incorporated

Inventor： Pritha Ghoshal ,  Niket Choudhary ,  Ravi Rajagopalan ,  Patrick Eibl ,  Brian Stempel ,  David Scott Ray ,  Thomas Philip Speier

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/1027

Abstract: A method, apparatus, and system for reducing pipeline stalls due to address translation misses is presented. An apparatus comprises a memory access instruction pipeline, a translation lookaside buffer coupled to the memory access instruction pipeline, and a TLB miss queue coupled to both the TLB and the memory access instruction pipeline. The TLB miss queue is configured to selectively store a first memory access instruction that has been removed from the memory access instruction pipeline as a result of the first memory access instruction missing in the TLB along with information associated with the first memory access instruction. The TLB miss queue is further configured to reintroduce the first memory access instruction to the memory access instruction pipeline associated with a return of an address translation related to the first memory access instruction.