公开(公告)号：US20240322837A1

公开(公告)日：2024-09-26

申请号：US18190033

申请日：2023-03-24

Applicant: QUALCOMM Incorporated

Inventor： Shashank Rajendra PRASAD ,  Xiaopeng ZHONG

IPC: H03M1/46

CPC classification number: H03M1/466

Abstract: Aspects of the present disclosure provide input-adaptive analog-to-digital conversion in which the number of conversion cycles used to convert an input signal into a digital signal is adapted based on the level (i.e., amplitude) of the input voltage. In certain aspects, the input voltage is compared with one or more threshold voltages, and the number of conversion cycles is determined based on the comparison. In certain aspects, a most significant bit (MSB) capacitor in a capacitive digital-to-analog (DAC) is split into two or more capacitors to provide the one or more threshold voltages.