公开(公告)号：US09379722B2

公开(公告)日：2016-06-28

申请号：US13926631

申请日：2013-06-25

Applicant: QUALCOMM Incorporated

Inventor： Wu-Hsin Chen ,  Sriramgopal Sridhara ,  Li Liu

IPC: H03K21/00 ,  H03K23/00 ,  H03K25/00 ,  H03L7/18 ,  H03K3/017 ,  H03K5/156 ,  H03K21/08

CPC classification number: H03L7/18 ,  H03K3/017 ,  H03K5/1565 ,  H03K21/08

Abstract: A frequency divider with duty cycle adjustment within a feedback loop is disclosed. In an exemplary design, an apparatus includes at least one divider circuit and at least one duty cycle adjustment circuit coupled in a feedback loop. The divider circuit(s) receive a clock signal at a first frequency and provide at least one divided signal at a second frequency, which is a fraction of the first frequency. The duty cycle adjustment circuit(s) adjust the duty cycle of the at least one divided signal and provide at least one duty cycle adjusted signal to the divider circuit(s). The divider circuit(s) may include first and second latches, and the duty cycle adjustment circuit(s) may include first and second duty cycle adjustment circuits. The first and second latches and the first and second duty cycle adjustment circuits may be coupled in a feedback loop and may perform divide-by-2.

Abstract translation: 公开了一种在反馈环路内进行占空比调节的分频器。 在示例性设计中，装置包括耦合在反馈回路中的至少一个除法器电路和至少一个占空比调整电路。 分频器电路以第一频率接收时钟信号，并以第二频率提供至少一个分频信号，该第二频率是第一频率的一部分。 占空比调整电路调整至少一个分频信号的占空比，并向分频器电路提供至少一个占空比调整信号。 分频器电路可以包括第一和第二锁存器，并且占空比调整电路可以包括第一和第二占空比调整电路。 第一和第二锁存器以及第一和第二占空比调整电路可以耦合在反馈回路中并且可以执行除以2。

公开(公告)号：US20140375363A1

公开(公告)日：2014-12-25

申请号：US13926631

申请日：2013-06-25

Applicant: QUALCOMM Incorporated

Inventor： Wu-Hsin Chen ,  Sriramgopal Sridhara ,  Li Liu

IPC: H03L7/18

CPC classification number: H03L7/18 ,  H03K3/017 ,  H03K5/1565 ,  H03K21/08

Abstract: A frequency divider with duty cycle adjustment within a feedback loop is disclosed. In an exemplary design, an apparatus includes at least one divider circuit and at least one duty cycle adjustment circuit coupled in a feedback loop. The divider circuit(s) receive a clock signal at a first frequency and provide at least one divided signal at a second frequency, which is a fraction of the first frequency. The duty cycle adjustment circuit(s) adjust the duty cycle of the at least one divided signal and provide at least one duty cycle adjusted signal to the divider circuit(s). The divider circuit(s) may include first and second latches, and the duty cycle adjustment circuit(s) may include first and second duty cycle adjustment circuits. The first and second latches and the first and second duty cycle adjustment circuits may be coupled in a feedback loop and may perform divide-by-2.

Abstract translation: 公开了一种在反馈环路内进行占空比调节的分频器。 在示例性设计中，装置包括耦合在反馈回路中的至少一个除法器电路和至少一个占空比调整电路。 分频器电路以第一频率接收时钟信号，并以第二频率提供至少一个分频信号，该第二频率是第一频率的一部分。 占空比调整电路调整至少一个分频信号的占空比，并向分频器电路提供至少一个占空比调整信号。 分频器电路可以包括第一和第二锁存器，并且占空比调整电路可以包括第一和第二占空比调整电路。 第一和第二锁存器以及第一和第二占空比调整电路可以耦合在反馈回路中并且可以执行除以2。

公开(公告)号：US20240097724A1

公开(公告)日：2024-03-21

申请号：US17933601

申请日：2022-09-20

Applicant: QUALCOMM Incorporated

Inventor： Roberto Rimini ,  Sriramgopal Sridhara

IPC: H04B1/04 ,  H03B5/12 ,  H03L7/099 ,  H03L7/24 ,  H04B1/16

CPC classification number: H04B1/0483 ,  H03B5/1228 ,  H03L7/099 ,  H03L7/24 ,  H04B1/1607 ,  H03B2200/0074

Abstract: An apparatus is disclosed for injecting a frequency-modulated signal into a receiver. In an example aspect, the apparatus includes a receiver, a local oscillator circuit, and an injection circuit. The receiver comprises a signal propagation path. The local oscillator circuit is configured to generate a frequency-modulated signal. The injection circuit is coupled to the receiver and the local oscillator circuit. The injection circuit is configured to selectively connect the local oscillator circuit to the signal propagation path of the receiver to inject the frequency-modulated signal into the signal propagation path of the receiver. The injection circuit is also configured to disconnect the local oscillator circuit from the signal propagation path of the receiver.