Display and automatic improvement of timing and area in a network-on-chip
    1.
    发明授权
    Display and automatic improvement of timing and area in a network-on-chip 有权
    显示和自动改进片上网络的时序和面积

    公开(公告)号:US09098658B2

    公开(公告)日:2015-08-04

    申请号:US13898540

    申请日:2013-05-21

    CPC classification number: G06F17/5031 G06F17/505 G06F2217/84

    Abstract: A method and NoC design tool is disclosed that automatically maps the paths listed in a timing report and the unit size in an area report to the topology of a NoC and displays the paths and unit sizes in a GUI. The tool can also automatically add pipeline stages, separated by the maximum delay allowed in the timing budget, in order to achieve timing closure in an automated way.

    Abstract translation: 公开了一种方法和NoC设计工具,其将定时报告中列出的路径和区域报告中的单位大小自动映射到NoC的拓扑,并在GUI中显示路径和单位大小。 该工具还可以自动添加流水线阶段,由时间预算允许的最大延迟分隔,以便以自动方式实现时序收敛。

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