公开(公告)号：US20240097880A1

公开(公告)日：2024-03-21

申请号：US18039865

申请日：2021-11-30

Applicant: RAMBUS INC.

Inventor： Pascal VAN LEEUWEN

IPC: H04L9/06

CPC classification number: H04L9/0631

Abstract: Disclosed embodiments relate to cipher accelerator circuit comprising: a first affine transformation circuit generating a first data block from an input data block, a SM4 S-box circuit configured to perform a first byte S-box operation according to a SM4 cipher and using a SM4 S-box table, the SM4 S-box operation being applied to the first transformed data block to obtain a substituted data block; and a second affine transformation circuit generating a second data block from the substituted data block, wherein the first and second affine transformation circuits are configured to perform multiplication of the substituted data block by a respective matrix and addition of a respective translation vector, and wherein the first and second affine transformations circuits are configured such that the second transformed data block is equal to the input data block processed by a second S-box operation according to another symmetric cipher using S-box tables.