公开(公告)号：US3878335A

公开(公告)日：1975-04-15

申请号：US40769673

申请日：1973-10-18

Applicant: RCA CORP

Inventor： BALABAN ALVIN REUBEN

IPC: H04N5/04 ,  H04N5/06 ,  H04N5/12 ,  H04M5/06

CPC classification number: H04N5/12

Abstract: A digital vertical deflection rate synchronization system includes a source of clock pulses which drives a divide-by-525 counter and a serial-to-parallel shift register. An incoming low frequency signal such as that obtained from the sync separator stage of a television receiver is scanned at the clock rate to determine whether it exhibits the width characteristic of the vertical sync signal. If the incoming signal does not, the vertical deflection sawtooth generator is synchronized by a pulse derived from the divide-by-525 counter. If the incoming signal does exhibit the vertical sync pulse width characteristic, it is allowed to reset the divide-by-525 counter. In the event that the divide-by-525 counter is reset before it has passed a synchronizing pulse to the vertical deflection sawtooth generator, an overscan limit control circuit senses the collapsing vertical deflection yoke field and creates a vertical deflection synchronizing pulse.

Abstract translation: 数字垂直偏转率同步系统包括驱动525分频计数器和串并行移位寄存器的时钟脉冲源。 以时钟速率扫描诸如从电视接收机的同步分离级获得的输入低频信号，以确定其是否呈现垂直同步信号的宽度特性。 如果输入信号没有，则垂直偏转锯齿波发生器通过从525分频计数器得到的脉冲同步。 如果输入信号确实表现出垂直同步脉冲宽度特性，则允许将525分频计数器复位。 在525分频计数器在通过同步脉冲到垂直偏转锯齿波发生器之前被复位的情况下，过扫描极限控制电路检测到塌陷的垂直偏转磁轭场并产生垂直偏转同步脉冲。

公开(公告)号：US3878336A

公开(公告)日：1975-04-15

申请号：US40770073

申请日：1973-10-18

Applicant: RCA CORP

Inventor： BALABAN ALVIN REUBEN

IPC: H04N5/04 ,  H04N5/06 ,  H04N5/08 ,  H04N5/12 ,  H04M5/06

CPC classification number: H04N5/12

Abstract: Frequency doubled television receiver horizontal deflection frequency signals are divided in a divide-by-525 counter to produce pulses at the vertical deflection rate. The five hundred twentieth pulse of each 525 pulse series is used to enable a bistable multivibrator which produces an enabling signal on an ''''and'''' gate. The five hundred twenty-fifth pulse of each 525 pulse series produces a resetting signal on an ''''or'''' gate. The fifth pulse of each 525 pulse series removes the enabling signal from the output terminal of the bistable multivibrator thereby inhibiting the and gate. The vertical sync pulse appearing between the five hundred twentieth pulse of each 525 pulse series and the fifth pulse of the next succeeding 525 pulse series passes through the enabled and gate and synchronizes the operation of the vertical deflection circuit. The vertical deflection sync pulse is also coupled to the or gate to reset the divide-by-525 counter and synchronize its operation to the incoming vertical sync.

Abstract translation: 频率双倍的电视接收机水平偏转频率信号被划分为525分频计数器，以产生垂直偏转率的脉冲。 每个525脉冲序列的第500个第50个脉冲用于使能在“和”门上产生使能信号的双稳态多谐振荡器。 每个525脉冲序列的第五百五十五个脉冲在“或”门上产生复位信号。 每个525脉冲序列的第五个脉冲从双稳态多谐振荡器的输出端去除使能信号，从而抑制和门极。 每个525脉冲序列的第500个第50个脉冲之间出现的垂直同步脉冲和下一个后续的525脉冲序列的第五个脉冲通过使能和门并同步垂直偏转电路的操作。 垂直偏转同步脉冲也耦合到或门以复位525分频计数器，并使其操作与进入的垂直同步同步。