公开(公告)号：US3919484A

公开(公告)日：1975-11-11

申请号：US44726674

申请日：1974-03-01

Applicant: RCA CORP

Inventor： MAXEMCHUK NICHOLAS FRANK

IPC: H04L12/42 ,  H04L25/24 ,  H04J3/08

CPC classification number: H04L25/242 ,  H04L12/422

Abstract: A loop controller for a time division multiplexed loop communications system. The loop controller is connected in series with a plurality of data processors in a loop configuration. The loop controller provides a certain number of time slots in a frame. The data processors communicate with each other in channels comprising two time slots. Each data processor must acquire the same channel in each frame. The loop controller provides an adaptive delay function such that the total delay around the loop is a multiple of the time slots forming a frame to insure that the data processors acquire the same channel in each frame. In addition, the loop controller re-times the signals circulating on the loop and detects and counts violations of the modulation rule utilized by the signals circulating on the loop.

Abstract translation: 一种用于时分复用回路通信系统的回路控制器。 环路控制器以环路配置与多个数据处理器串联连接。 环路控制器在帧中提供一定数量的时隙。 数据处理器在包括两个时隙的信道中彼此通信。 每个数据处理器必须在每个帧中获得相同的通道。 环路控制器提供自适应延迟功能，使得环路周围的总延迟是形成帧的时隙的倍数，以确保数据处理器在每帧中获取相同的信道。 此外，环路控制器重新循环在循环上循环的信号，并检测和计数违反循环中循环的信号所使用的调制规则。

公开(公告)号：US3879582A

公开(公告)日：1975-04-22

申请号：US44726574

申请日：1974-03-01

Applicant: RCA CORP

Inventor： WHITE HUGH EDWARD ,  MAXEMCHUK NICHOLAS FRANK

IPC: H04L12/437 ,  H04L25/02 ,  H04J3/08

CPC classification number: H04L12/437 ,  H04L25/0262

Abstract: A loop digital data communications system in which a plurality of data processing units are connected in series with each other in the loop. Each data processor has a terminal device associated therewith for providing and receiving digital signals. The loop system also includes a loop controller connected in series in the loop with the data processors. The controller provides framed time division multiplexed channels for communication between terminal devices and a loop time delay to insure that each of the data processor transmits and receives signals in a selected channel over successive frames. The data processors are arranged to handle a plurality of synchronous data rates so that terminal devices at a plurality of data rates are serviced by the loop system. In addition, the data processors include a sampling technique so that asynchronous terminal devices may also be utilized with the system.

Abstract translation: 一种循环数字数据通信系统，其中多个数据处理单元在循环中彼此串联连接。 每个数据处理器具有与其相关联的终端设备，用于提供和接收数字信号。 环路系统还包括一个与数据处理器在环路中串联连接的环路控制器。 控制器提供用于终端设备之间通信的帧时分多路复用通道和循环时间延迟，以确保数据处理器中的每一个在连续的帧上以所选通道发送和接收信号。 数据处理器被布置为处理多个同步数据速率，使得以多个数据速率的终端设备由循环系统服务。 此外，数据处理器包括采样技术，使得异步终端设备也可以与系统一起使用。