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1.发明授权Concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers 失效在跟踪过程和使用可编程可变数量的共享内存写入缓冲区的非跟踪过程之间同时共享内存控制器公开(公告)号：US07913123B2
公开(公告)日：2011-03-22
申请号：US12210005
申请日：2008-09-12
IPC分类号： G06F11/00
CPC分类号： G06F11/2268 , G06F11/348
摘要： An apparatus and computer program product are disclosed for, in a processor, concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers. A hardware trace facility captures hardware trace data in a processor. The hardware trace facility is included within the processor. The hardware trace data is transmitted to a system memory utilizing a system bus. The system memory is included within the system. The system bus is capable of being utilized by processing units included in the processing node while the hardware trace data is being transmitted to the system bus. Part of system memory is utilized to store the trace data. The system memory is capable of being accessed by processing units in the processing node other than the hardware trace facility while part of the system memory is being utilized to store the trace data.
摘要翻译： 公开了一种装置和计算机程序产品，用于在处理器中使用可编程可变数量的共享存储器写缓冲器在跟踪处理和非跟踪处理之间共享存储器控制器。 硬件跟踪设备捕获处理器中的硬件跟踪数据。 硬件跟踪工具包含在处理器内。 使用系统总线将硬件跟踪数据传输到系统存储器。 系统内存包含在系统中。 当将硬件跟踪数据发送到系统总线时，系统总线能够被包括在处理节点中的处理单元利用。 系统内存的一部分用于存储跟踪数据。 系统存储器能够被处理节点除硬件跟踪设备之外的处理单元访问，同时系统存储器的一部分用于存储跟踪数据。
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2.发明申请Method, Apparatus, and Computer Program Product in a Processor for Dynamically During Runtime Allocating Memory for In-Memory Hardware Tracing 有权处理器中的方法，设备和计算机程序产品在运行时间内动态分配内存用于内存中硬件跟踪公开(公告)号：US20090031173A1
公开(公告)日：2009-01-29
申请号：US12206967
申请日：2008-09-09
CPC分类号： G06F11/2268 , G06F11/3476 , G06F11/348
摘要： A method, apparatus, and computer program product are disclosed in a processor for dynamically, during runtime, allocating memory for in-memory hardware tracing. The processor is included within a data processing system. The processor includes multiple processing units that are coupled together utilizing a system bus. The processing units include a memory controller that controls a system memory. A particular size of the system memory is determined that is needed for storing trace data. A hardware trace facility requests, dynamically after the data processing system has completed booting, the particular size of the system memory to be allocated to the hardware trace facility for storing trace data that is captured by the hardware trace facility. The firmware selects particular locations within the system memory. All of the particular locations together are the particular size. The firmware allocates the particular locations for use exclusively by the hardware trace facility.
摘要翻译： 在处理器中公开了一种方法，装置和计算机程序产品，用于在运行时期间动态地为存储器内硬件跟踪分配存储器。 处理器包含在数据处理系统中。 处理器包括使用系统总线耦合在一起的多个处理单元。 处理单元包括控制系统存储器的存储器控制器。 确定存储跟踪数据所需的特定大小的系统存储器。 硬件跟踪设施在数据处理系统完成启动之后动态地请求要分配给硬件跟踪设备的系统内存的特定大小，用于存储由硬件跟踪设备捕获的跟踪数据。 固件选择系统内存中的特定位置。 所有特定位置在一起是特定的尺寸。 固件分配由硬件跟踪设备专门使用的特定位置。
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3.发明授权Method, apparatus, and computer program product in a processor for concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers 失效处理器中的方法，装置和计算机程序产品，用于在跟踪过程和使用可编程可变数量的共享存储器写入缓冲器的非跟踪处理之间并发共享存储器控制器公开(公告)号：US07437617B2
公开(公告)日：2008-10-14
申请号：US11055845
申请日：2005-02-11
IPC分类号： G06F11/00
CPC分类号： G06F11/2268 , G06F11/348
摘要： A method, apparatus, and computer program product are disclosed for, in a processor, concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers. A hardware trace facility captures hardware trace data in a processor. The hardware trace facility is included within the processor. The hardware trace data is transmitted to a system memory utilizing a system bus. The system memory is included within the system. The system bus is capable of being utilized by processing units included in the processing node while the hardware trace data is being transmitted to the system bus. Part of system memory is utilized to store the trace data. The system memory is capable of being accessed by processing units in the processing node other than the hardware trace facility while part of the system memory is being utilized to store the trace data.
摘要翻译： 公开了一种方法，装置和计算机程序产品，用于在处理器中使用可编程可变数量的共享存储器写缓冲器在跟踪处理和非跟踪处理之间共享存储器控制器。 硬件跟踪设备捕获处理器中的硬件跟踪数据。 硬件跟踪工具包含在处理器内。 使用系统总线将硬件跟踪数据传输到系统存储器。 系统内存包含在系统中。 当将硬件跟踪数据发送到系统总线时，系统总线能够被包括在处理节点中的处理单元利用。 系统内存的一部分用于存储跟踪数据。 系统存储器能够被处理节点除硬件跟踪设备之外的处理单元访问，同时系统存储器的一部分用于存储跟踪数据。
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4.发明申请Apparatus and Computer Program Product in a Processor for Performing In-Memory Tracing Using Existing Communication Paths 失效用于使用现有通信路径执行内存中跟踪的处理器中的设备和计算机程序产品公开(公告)号：US20090024878A1
公开(公告)日：2009-01-22
申请号：US12201557
申请日：2008-08-29
CPC分类号： G06F11/2268 , G06F11/348
摘要： An apparatus and computer program product are disclosed for performing in-memory hardware tracing in a processor using an existing system bus. The processor includes multiple processing units that are coupled together utilizing the system bus. The processing units include a memory controller that controls a system memory. Information is transmitted among the processing units utilizing the system bus. The information is formatted according to a standard system bus protocol. Hardware trace data is captured utilizing a hardware trace facility that is coupled directly to the system bus. The system bus is utilized for transmitting the hardware trace data to the memory controller for storage in the system memory. The memory controller is coupled directly to the system bus. The hardware trace data is formatted according to the standard system bus protocol for transmission via the system bus.
摘要翻译： 公开了一种用于使用现有系统总线在处理器中执行存储器内硬件跟踪的装置和计算机程序产品。 处理器包括利用系统总线耦合在一起的多个处理单元。 处理单元包括控制系统存储器的存储器控制器。 利用系统总线在处理单元之间传送信息。 信息根据标准系统总线协议进行格式化。 使用直接耦合到系统总线的硬件跟踪功能来捕获硬件跟踪数据。 系统总线用于将硬件跟踪数据发送到存储器控制器以存储在系统存储器中。 存储器控制器直接耦合到系统总线。 硬件跟踪数据根据标准系统总线协议进行格式化，以便通过系统总线进行传输。
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5.发明申请Method, Apparatus, and Computer Program Product in a Processor for Concurrently Sharing a Memory Controller Among a Tracing Process and Non-Tracing Processes Using a Programmable Variable Number of Shared Memory Write Buffers 失效处理器中的方法，装置和计算机程序产品，用于在使用可编程可变数量的共享存储器写缓冲器的跟踪处理和非跟踪过程中并发共享存储器控制器公开(公告)号：US20090006825A1
公开(公告)日：2009-01-01
申请号：US12210005
申请日：2008-09-12
IPC分类号： G06F9/30
CPC分类号： G06F11/2268 , G06F11/348
摘要： A method, apparatus, and computer program product are disclosed for, in a processor, concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers. A hardware trace facility captures hardware trace data in a processor. The hardware trace facility is included within the processor. The hardware trace data is transmitted to a system memory utilizing a system bus. The system memory is included within the system. The system bus is capable of being utilized by processing units included in the processing node while the hardware trace data is being transmitted to the system bus. Part of system memory is utilized to store the trace data. The system memory is capable of being accessed by processing units in the processing node other than the hardware trace facility while part of the system memory is being utilized to store the trace data.
摘要翻译： 公开了一种方法，装置和计算机程序产品，用于在处理器中使用可编程可变数量的共享存储器写缓冲器在跟踪处理和非跟踪处理之间共享存储器控制器。 硬件跟踪设备捕获处理器中的硬件跟踪数据。 硬件跟踪工具包含在处理器内。 使用系统总线将硬件跟踪数据传输到系统存储器。 系统内存包含在系统中。 当硬件跟踪数据被传送到系统总线时，系统总线能够被包括在处理节点中的处理单元利用。 系统内存的一部分用于存储跟踪数据。 系统存储器能够被处理节点除硬件跟踪设备之外的处理单元访问，同时系统存储器的一部分用于存储跟踪数据。
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6.发明授权Method in a processor for dynamically during runtime allocating memory for in-memory hardware tracing 失效处理器中的方法在运行时动态地分配用于内存中硬件跟踪的存储器公开(公告)号：US07437618B2
公开(公告)日：2008-10-14
申请号：US11055977
申请日：2005-02-11
IPC分类号： G06F11/00
CPC分类号： G06F11/2268 , G06F11/3476 , G06F11/348
摘要： A method, apparatus, and computer program product are disclosed in a processor for dynamically, during runtime, allocating memory for in-memory hardware tracing. The processor is included within a data processing system. The processor includes multiple processing units that are coupled together utilizing a system bus. The processing units include a memory controller that controls a system memory. A particular size of the system memory is determined that is needed for storing trace data. A hardware trace facility requests, dynamically after the data processing system has completed booting, the particular size of the system memory to be allocated to the hardware trace facility for storing trace data that is captured by the hardware trace facility. The firmware selects particular locations within the system memory. All of the particular locations together are the particular size. The firmware allocates the particular locations for use exclusively by the hardware trace facility.
摘要翻译： 在处理器中公开了一种方法，装置和计算机程序产品，用于在运行时期间动态地为存储器内硬件跟踪分配存储器。 处理器包含在数据处理系统中。 处理器包括使用系统总线耦合在一起的多个处理单元。 处理单元包括控制系统存储器的存储器控制器。 确定存储跟踪数据所需的特定大小的系统存储器。 硬件跟踪设施在数据处理系统完成启动之后动态地请求要分配给硬件跟踪设备的系统内存的特定大小，用于存储由硬件跟踪设备捕获的跟踪数据。 固件选择系统内存中的特定位置。 所有特定位置在一起是特定的尺寸。 固件分配由硬件跟踪设备专门使用的特定位置。
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7.发明授权Method in a processor for performing in-memory tracing using existing communication paths 失效用于使用现有通信路径执行内存中跟踪的处理器中的方法公开(公告)号：US07421619B2
公开(公告)日：2008-09-02
申请号：US11055821
申请日：2005-02-11
IPC分类号： G06F11/00
CPC分类号： G06F11/2268 , G06F11/348
摘要： A method, apparatus, and computer program product are disclosed for performing in-memory hardware tracing in a processor using an existing system bus. The processor includes multiple processing units that are coupled together utilizing the system bus. The processing units include a memory controller that controls a system memory. Information is transmitted among the processing units utilizing the system bus. The information is formatted according to a standard system bus protocol. Hardware trace data is captured utilizing a hardware trace facility that is coupled directly to the system bus. The system bus is utilized for transmitting the hardware trace data to the memory controller for storage in the system memory. The memory controller is coupled directly to the system bus. The hardware trace data is formatted according to the standard system bus protocol for transmission via the system bus.
摘要翻译： 公开了一种用于使用现有系统总线在处理器中执行存储器内硬件跟踪的方法，装置和计算机程序产品。 处理器包括利用系统总线耦合在一起的多个处理单元。 处理单元包括控制系统存储器的存储器控制器。 利用系统总线在处理单元之间传送信息。 信息根据标准系统总线协议进行格式化。 使用直接耦合到系统总线的硬件跟踪功能来捕获硬件跟踪数据。 系统总线用于将硬件跟踪数据发送到存储器控制器以存储在系统存储器中。 存储器控制器直接耦合到系统总线。 硬件跟踪数据根据标准系统总线协议进行格式化，以便通过系统总线进行传输。
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8.发明授权Synchronizing triggering of multiple hardware trace facilities using an existing system bus 失效使用现有系统总线同步触发多个硬件跟踪工具公开(公告)号：US07418629B2
公开(公告)日：2008-08-26
申请号：US11055870
申请日：2005-02-11
IPC分类号： G06F11/00
CPC分类号： G06F11/2268 , G06F11/348
摘要： A method, apparatus, and computer program product are disclosed in a data processing system for synchronizing the triggering of multiple hardware trace facilities using an existing bus. The multiple hardware trace facilities include a first hardware trace facility and a second hardware trace facility. The data processing system includes a first processor that includes the first hardware trace facility and first processing units that are coupled together utilizing the system bus, and a second processor that includes the second hardware trace facility and second processing units that are coupled together utilizing the system bus. Information is transmitted among the first and second processing units utilizing the system bus when the processors are in a normal, non-tracing mode, where the information is formatted according to a standard system bus protocol. Trigger events are transmitted to the hardware trace facilities utilizing the same standard system bus, where the trigger events are also formatted according to the standard system bus protocol.
摘要翻译： 在用于使用现有总线触发多个硬件跟踪设备的数据处理系统中公开了一种方法，装置和计算机程序产品。 多个硬件跟踪设备包括第一个硬件跟踪设备和第二个硬件跟踪设备。 数据处理系统包括第一处理器，其包括第一硬件跟踪设备和利用系统总线耦合在一起的第一处理单元，以及包括第二硬件跟踪设备的第二处理器和利用系统耦合在一起的第二处理单元 总线。 当处理器处于正常的非跟踪模式时，利用系统总线在第一和第二处理单元之间传送信息，其中信息根据标准系统总线协议被格式化。 触发事件使用相同的标准系统总线传输到硬件跟踪设备，触发事件也根据标准系统总线协议进行格式化。
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公开(公告)号：US20090106588A1
公开(公告)日：2009-04-23
申请号：US11874232
申请日：2007-10-18
申请人： Patrick J. Meaney , Ra'ed Mohammad Al-Omari , Michael Francis Fee , Pak-kin Mak , Scott Barnett Swaney
发明人： Patrick J. Meaney , Ra'ed Mohammad Al-Omari , Michael Francis Fee , Pak-kin Mak , Scott Barnett Swaney
CPC分类号： G06F11/10
摘要： A method and apparatus are disclosed for performing maintenance operations in a system using address, data, and controls which are transported through the system, allowing for parallel and serial operations to co-exist without the parallel operations being slowed down by the serial ones. It also provides for use of common shifters, engines, and protocols as well as efficient conversion of ECC to parity and parity to ECC as needed in the system. The invention also provides for error detection and isolation, both locally and in the reported status. The invention provides for large maintenance address and data spaces (typically 64 bits address and 64 bits data per address supported).
摘要翻译： 公开了一种用于在通过系统传送的地址，数据和控制的系统中进行维护操作的方法和装置，允许并行和串行操作共存，而并行操作不被串行操作减慢。 它还提供了常用的移位器，引擎和协议的使用，以及系统中根据需要将ECC高效地转换为奇偶校验和奇偶校验。 本发明还提供了本地和报告状态的错误检测和隔离。 本发明提供大的维护地址和数据空间（通常支持64位地址和64位数据）。
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公开(公告)号：US08122297B2
公开(公告)日：2012-02-21
申请号：US11874232
申请日：2007-10-18
申请人： Patrick J. Meaney , Ra'ed Mohammad Al-Omari , Michael Francis Fee , Pak-kin Mak , Scott Barnett Swaney
发明人： Patrick J. Meaney , Ra'ed Mohammad Al-Omari , Michael Francis Fee , Pak-kin Mak , Scott Barnett Swaney
IPC分类号： G06F11/00
CPC分类号： G06F11/10
摘要： A method and apparatus are disclosed for performing maintenance operations in a system using address, data, and controls which are transported through the system, allowing for parallel and serial operations to co-exist without the parallel operations being slowed down by the serial ones. It also provides for use of common shifters, engines, and protocols as well as efficient conversion of ECC to parity and parity to ECC as needed in the system. The invention also provides for error detection and isolation, both locally and in the reported status. The invention provides for large maintenance address and data spaces (typically 64 bits address and 64 bits data per address supported).
摘要翻译： 公开了一种用于在通过系统传送的地址，数据和控制的系统中进行维护操作的方法和装置，允许并行和串行操作共存，而并行操作不被串行操作减慢。 它还提供了常用的移位器，引擎和协议的使用，以及系统中根据需要将ECC高效地转换为奇偶校验和奇偶校验。 本发明还提供了本地和报告状态的错误检测和隔离。 本发明提供大的维护地址和数据空间（通常支持64位地址和64位数据）。
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