Chip sizing for hierarchical designs
    1.
    发明授权
    Chip sizing for hierarchical designs 失效
    分层设计的芯片尺寸

    公开(公告)号:US5731985A

    公开(公告)日:1998-03-24

    申请号:US631113

    申请日:1996-04-23

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5072

    摘要: A method for resizing the macro cells' boundaries of an integrated chip is disclosed and that becomes effectual after the initial floorplanning process has been completed. The method of the present invention apportions any excess area that is freed-up after the initial floorplanning process by altering the sizes or dimensions of the macro cell within the hierarchy of the integrated circuit in such a manner that the fractional change in the percentage occupancy is substantially constant among all macro cells at all hierarchy levels.

    摘要翻译: 公开了一种用于调整集成芯片的宏单元边界的大小的方法,并且在初始布局规划过程完成之后变得有效。 本发明的方法通过在集成电路的层次结构中改变宏小区的大小或尺寸,使得百分比占有率的分数变化是这样的方式来分配在初始布局规划过程之后释放的任何多余区域: 在所有层次级别的所有宏小区中基本恒定。

    Decision support activation and management in product life cycles using a context pyramid structure
    2.
    发明授权
    Decision support activation and management in product life cycles using a context pyramid structure 有权
    决策支持使用上下文金字塔结构在产品生命周期中激活和管理

    公开(公告)号:US07729933B2

    公开(公告)日:2010-06-01

    申请号:US10699020

    申请日:2003-10-31

    IPC分类号: G06Q10/00

    摘要: Techniques are provided for product life cycle management over an information network. More particularly, techniques are provided for decision support activation and management in accordance with a product life cycle management process such as a collaborative design process. In one aspect of the invention, a technique for managing at least one collaborative process performed in accordance with a first entity and at least a second entity, comprises the following steps/operations. Information associated with the at least one collaborative process is obtained. Based on at least a portion of the obtained information, an information structure (e.g., a context pyramid) representative of the collaborative process is dynamically maintained so as to assist at least one of the first entity and the second entity in managing at least a portion of the collaborative process.

    摘要翻译: 提供了通过信息网络进行产品生命周期管理的技术。 更具体地,根据诸如协作设计过程的产品生命周期管理过程,提供用于决策支持激活和管理的技术。 在本发明的一个方面,一种用于管理根据第一实体和至少第二实体执行的至少一个协作过程的技术包括以下步骤/操作。 获得与至少一个协作过程相关联的信息。 基于获得的信息的至少一部分,动态地维护代表协作过程的信息结构(例如,上下文金字塔),以便协助第一实体和第二实体中的至少一个管理至少一部分 的合作过程。

    Method and Apparatus for Dynamic Device Allocation for Managing Escalation of On-Demand Business Processes
    3.
    发明申请
    Method and Apparatus for Dynamic Device Allocation for Managing Escalation of On-Demand Business Processes 审中-公开
    用于管理按需业务流程升级的动态设备分配的方法和装置

    公开(公告)号:US20080244610A1

    公开(公告)日:2008-10-02

    申请号:US12137181

    申请日:2008-06-11

    IPC分类号: G06F9/46

    摘要: Resource allocation techniques are provided for use in managing escalation of on-demand business processes. For example, in one aspect of the invention, a technique for managing escalation of a business process comprises the following steps/operations. A request is obtained from a business process, the business process having one or more tasks associated therewith. The one or more tasks are mapped to one or more roles. One or more available resources are allocated for the one or more roles. At least one communication session is launched such that data associated with the business process may be transferred to the one or more allocated resources.

    摘要翻译: 提供了资源分配技术,用于管理按需业务流程的升级。 例如,在本发明的一个方面,一种用于管理业务流程升级的技术包括以下步骤/操作。 从业务流程获得请求,该业务流程具有与其相关联的一个或多个任务。 一个或多个任务映射到一个或多个角色。 为一个或多个角色分配一个或多个可用资源。 启动至少一个通信会话,使得与业务过程相关联的数据可以被传送到一个或多个分配的资源。

    Method and apparatus for placing and detecting prewire blockages of
library cells
    5.
    发明授权
    Method and apparatus for placing and detecting prewire blockages of library cells 失效
    用于放置和检测文库细胞的prewire阻塞的方法和装置

    公开(公告)号:US5793641A

    公开(公告)日:1998-08-11

    申请号:US576187

    申请日:1995-12-21

    IPC分类号: G06F17/50 G06F15/00

    CPC分类号: G06F17/5068

    摘要: A method and apparatus for detecting valid placement of library cells on chip images or hierarchy design images may be accomplished by determining a periodic pattern of the chip image, or hierarchical image. Once the repetitive pattern is recognized, this pattern is represented by a binary vector. Similarly, a binary vector is created for a particular cell library that is to be placed on the chip image or hierarchical design image. When the placement algorithm places the library cell on the chip or hierarchical image, the binary vector of the library cell is folded over a folded binary vector of the chip image or hierarchical design image to produce a component delta set. In essence, the component delta set indicates spacing violations between the library cell and the chip or hierarchical design image. When such a spacing violation is recognized, the placement algorithm can immediately reposition the library cell.

    摘要翻译: 可以通过确定芯片图像或分层图像的周期性图案来实现用于检测芯片图像或层次结构设计图像上的库单元的有效放置的方法和装置。 一旦重复模式被识别,该模式由二进制向量表示。 类似地,为要放置在芯片图像或分层设计图像上的特定单元库创建二进制向量。 当放置算法将库单元放置在芯片或分层图像上时,库单元的二进制向量在芯片图像或分层设计图像的折叠二进制向量上折叠以产生分量增量集。 本质上,组件增量集指示库单元与芯片或分层设计图像之间的间隔冲突。 当识别到这样的间隔冲突时,放置算法可以立即重新定位库单元。