公开(公告)号：US20130138927A1

公开(公告)日：2013-05-30

申请号：US13751324

申请日：2013-01-28

申请人： Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  Carlos Alba Pinto ,  Harm Peters ,  Rafael Peset LLopis

发明人： Ramanathan Sethuraman ,  Balakrishnan Srinivasan ,  Carlos Alba Pinto ,  Harm Peters ,  Rafael Peset LLopis

IPC分类号： G06F9/30

CPC分类号： G06F9/30003 ,  G06F9/30149 ,  G06F9/3802 ,  G06F9/3853

摘要： A data processing apparatus has an instruction memory system arranged to output an instruction word addressed by an instruction address. An instruction execution unit, processes a plurality of instructions from the instruction word in parallel. A detection unit, detects in which of a plurality of ranges the instruction address lies. The detection unit is coupled to the instruction execution unit and/or the instruction memory system, to control a way in which the instruction execution unit parallelizes processing of the instructions from the instruction word, dependent on a detected range. In an embodiment the instruction execution unit and/or the instruction memory system adjusts a width of the instruction word that determines a number of instructions from the instruction word that is processed in parallel, dependent on the detected range.

摘要翻译： 数据处理装置具有布置成输出由指令地址寻址的指令字的指令存储器系统。 指令执行单元，并行地从指令字处理多个指令。 检测单元，检测指示地址所在的多个范围中的哪一个。 检测单元耦合到指令执行单元和/或指令存储器系统，以根据检测到的范围来控制指令执行单元将来自指令字的指令的处理并行化的方式。 在一个实施例中，指令执行单元和/或指令存储器系统根据检测到的范围来调整从并行处理的指令字确定指令字数的指令字的宽度。