-
公开(公告)号：US20210091980A1
公开(公告)日：2021-03-25
申请号：US17068483
申请日：2020-10-12
Applicant: Rambus Inc.
Inventor： Kamran FARZAN , Aaron ALI
Abstract: A hybrid voltage mode (VM) and current mode (CM) four-level pulse amplitude modulation (PAM-4) transmitter circuits (a.k.a. drivers) is calibrated using a configurable replica circuit and calibration control circuitry. The replica circuit includes an on-chip termination impedance to mimic a receiver's termination impedance. The amount of level enhancement provided by the current mode circuitry is calibrated by adjusting the current provided to the output node and sunk from the output node by the replica current mode circuitry while the replica voltage mode circuitry is driving an intermediate PAM-4 level. After the level enhancement has been set, the non-linearity between levels is calibrated by adjusting the amount of current provided to the output node by the replica current mode circuitry while the replica voltage mode circuitry is driving a maximum output voltage level.
-
公开(公告)号：US20210248031A1
公开(公告)日：2021-08-12
申请号：US16973142
申请日：2019-06-14
Applicant: Rambus Inc.
Inventor： Angus William McLAREN , Robert A. HEATON , Aaron ALI , Frederick A. WARE
Abstract: A first serializing stage is provided with a stream of data words composed of sub-words that each have values that associate each of the sub-words with the same error detection code value. For example, the values selected for each sub-word may each be associated with even parity. One or more serializing stages time-multiplex the sub-words into a stream of sub-word sized data. At the serializing stage that receives sub-word sized data stream, the data is checked to determine whether any of the sub-words is no longer associated with the error detection code value. Serializing/deserializing stages are selectively controlled to replace one or more data bits from a word being serialized/deserialized with an error detecting code value (e.g., parity). A subsequent serializing/deserializing stage is enabled to use the inserted error detecting code values and the data in the received words to determine whether an error has occurred.
-
公开(公告)号：US20220374306A1
公开(公告)日：2022-11-24
申请号：US17840153
申请日：2022-06-14
Applicant: Rambus Inc.
Inventor： Angus William McLAREN , Robert A. HEATON , Aaron ALI , Frederick A. WARE
Abstract: A first serializing stage is provided with a stream of data words composed of sub-words that each have values that associate each of the sub-words with the same error detection code value. For example, the values selected for each sub-word may each be associated with even parity. One or more serializing stages time-multiplex the sub-words into a stream of sub-word sized data. At the serializing stage that receives sub-word sized data stream, the data is checked to determine whether any of the sub-words is no longer associated with the error detection code value. Serializing/deserializing stages are selectively controlled to replace one or more data bits from a word being serialized/deserialized with an error detecting code value (e.g., parity). A subsequent serializing/deserializing stage is enabled to use the inserted error detecting code values and the data in the received words to determine whether an error has occurred.
-
公开(公告)号：US20190394071A1
公开(公告)日：2019-12-26
申请号：US16441692
申请日：2019-06-14
Applicant: Rambus Inc.
Inventor： Kamran FARZAN , Aaron ALI
Abstract: A hybrid voltage mode (VM) and current mode (CM) four-level pulse amplitude modulation (PAM-4) transmitter circuits (a.k.a. drivers) is calibrated using a configurable replica circuit and calibration control circuitry. The replica circuit includes an on-chip termination impedance to mimic a receiver's termination impedance. The amount of level enhancement provided by the current mode circuitry is calibrated by adjusting the current provided to the output node and sunk from the output node by the replica current mode circuitry while the replica voltage mode circuitry is driving an intermediate PAM-4 level. After the level enhancement has been set, the non-linearity between levels is calibrated by adjusting the amount of current provided to the output node by the replica current mode circuitry while the replica voltage mode circuitry is driving a maximum output voltage level.
-
-
-
Search Results
4
records
(took 0.01 seconds)
