公开(公告)号：US20210281449A1

公开(公告)日：2021-09-09

申请号：US17181883

申请日：2021-02-22

Applicant: Rambus Inc.

Inventor： Nanyan WANG ,  Vadim MOSHINSKY ,  Prashant CHOUDHARY

IPC: H04L25/03 ,  H04L27/02

Abstract: Optimized continuous time linear equalization (CTLE) circuit parameters for a received signal are found using an iterative search process. The received signal is repeatedly sampled by an analog-to-digital converter (ADC). Certain samples containing interference that cannot be cancelled by a CTLE in the sampled series are filtered out (discarded). The remaining samples are used to generate, over a selected evaluation window, a histogram of the sampled values. This histogram is used to calculate a figure of merit for the current CTLE parameter settings. The figures of merit for various CTLE parameter settings are compared to find the set of CTLE parameter settings that optimize the figure of merit and by extension, optimize the CTLE circuitry's performance at equalizing the received signal.

公开(公告)号：US20210184711A1

公开(公告)日：2021-06-17

申请号：US17106641

申请日：2020-11-30

Applicant: Rambus Inc.

Inventor： Nanyan WANG ,  Marcus VAN IERSSEL

IPC: H04B1/16

Abstract: An integrated circuit that includes a feedback loop to adapt receiver parameters. The feedback loop includes a receiver to sample a signal and produce a sampled signal sequence. The feedback loop also includes a first pattern counter to detect and count occurrences of a first pattern in the sampled signal sequence, and a second pattern counter to detect and count occurrences of a second pattern in the sampled signal sequence. Control circuitry coupled to the receiver adapts a parameter value of the receiver to minimize a difference between a first ratio and a second ratio. The first ratio is a target ratio. The second ratio is between a first counted number of occurrences of the first pattern in the sampled signal sequence and a second counted number of occurrences of the second pattern in the sample signal sequence.

公开(公告)号：US20230231589A1

公开(公告)日：2023-07-20

申请号：US18096661

申请日：2023-01-13

Applicant: Rambus Inc.

Inventor： Nanyan WANG ,  Marcus VAN IERSSEL

IPC: H04B1/16

CPC classification number: H04B1/16

Abstract: An integrated circuit that includes a feedback loop to adapt receiver parameters. The feedback loop includes a receiver to sample a signal and produce a sampled signal sequence. The feedback loop also includes a first pattern counter to detect and count occurrences of a first pattern in the sampled signal sequence, and a second pattern counter to detect and count occurrences of a second pattern in the sampled signal sequence. Control circuitry coupled to the receiver adapts a parameter value of the receiver to minimize a difference between a first ratio and a second ratio. The first ratio is a target ratio. The second ratio is between a first counted number of occurrences of the first pattern in the sampled signal sequence and a second counted number of occurrences of the second pattern in the sample signal sequence.

公开(公告)号：US20220217025A1

公开(公告)日：2022-07-07

申请号：US17576501

申请日：2022-01-14

Applicant: Rambus Inc.

Inventor： Nanyan WANG ,  Vadim MOSHINSKY ,  Prashant CHOUDHARY

IPC: H04L25/03 ,  H04L27/02

Abstract: Optimized continuous time linear equalization (CTLE) circuit parameters for a received signal are found using an iterative search process. The received signal is repeatedly sampled by an analog-to-digital converter (ADC). Certain samples containing interference that cannot be cancelled by a CTLE in the sampled series are filtered out (discarded). The remaining samples are used to generate, over a selected evaluation window, a histogram of the sampled values. This histogram is used to calculate a figure of merit for the current CTLE parameter settings. The figures of merit for various CTLE parameter settings are compared to find the set of CTLE parameter settings that optimize the figure of merit and by extension, optimize the CTLE circuitry's performance at equalizing the received signal.