Memory repair systems and methods for a memory having redundant memory
    1.
    发明授权
    Memory repair systems and methods for a memory having redundant memory 有权
    具有冗余存储器的存储器的内存修复系统和方法

    公开(公告)号:US08659961B2

    公开(公告)日:2014-02-25

    申请号:US13619363

    申请日:2012-09-14

    IPC分类号: G11C7/00

    摘要: Memories, memory repair logic, and methods for repairing a memory having redundant memory are disclosed. One such memory includes programmable elements associated with respective redundant memory configured to have memory addresses mapped thereto, the programmable elements configured to be programmed with at least portions of the memory addresses. Such a memory further includes repair logic coupled to the programmable elements and configured to identify programmable elements available for programming to map memory addresses to respective redundant memory. One method for remapping a memory address of a memory to redundant memory includes receiving at least a portion of a memory address to be remapped to redundant memory, determining whether a programmable element associated with the redundant memory is available for programming, and when a programmable element is available, programming the programmable element such that the memory address will be mapped to the associated redundant memory.

    摘要翻译: 公开了用于修复具有冗余存储器的存储器的存储器,存储器修复逻辑和方法。 一个这样的存储器包括与被配置为具有映射到其上的存储器地址的相应冗余存储器相关联的可编程元件,所述可编程元件被配置为用至少部分存储器地址进行编程。 这种存储器还包括耦合到可编程元件的修复逻辑,并且被配置为识别可用于编程以将存储器地址映射到相应冗余存储器的可编程元件。 将存储器的存储器地址重新映射到冗余存储器的一种方法包括:接收要重新映射到冗余存储器的存储器地址的至少一部分,确定与冗余存储器相关联的可编程元件是否可用于编程,以及当可编程元件 是可用的,编程可编程元件,使得存储器地址将映射到相关联的冗余存储器。

    Memory repair systems and methods for a memory having redundant memory
    2.
    发明授权
    Memory repair systems and methods for a memory having redundant memory 有权
    具有冗余存储器的存储器的内存修复系统和方法

    公开(公告)号:US08289790B2

    公开(公告)日:2012-10-16

    申请号:US12779597

    申请日:2010-05-13

    IPC分类号: G11C7/00

    摘要: Memories, memory repair logic, and methods for repairing a memory having redundant memory are disclosed. One such memory includes programmable elements associated with respective redundant memory configured to have memory addresses mapped thereto, the programmable elements configured to be programmed with at least portions of the memory addresses. Such a memory further includes repair logic coupled to the programmable elements and configured to identify programmable elements available for programming to map memory addresses to respective redundant memory. One method for remapping a memory address of a memory to redundant memory includes receiving at least a portion of a memory address to be remapped to redundant memory, determining whether a programmable element associated with the redundant memory is available for programming, and when a programmable element is available, programming the programmable element such that the memory address will be mapped to the associated redundant memory.

    摘要翻译: 公开了用于修复具有冗余存储器的存储器的存储器,存储器修复逻辑和方法。 一个这样的存储器包括与被配置为具有映射到其上的存储器地址的相应冗余存储器相关联的可编程元件,所述可编程元件被配置为用至少部分存储器地址进行编程。 这种存储器还包括耦合到可编程元件的修复逻辑,并且被配置为识别可用于编程以将存储器地址映射到相应冗余存储器的可编程元件。 将存储器的存储器地址重新映射到冗余存储器的一种方法包括:接收要重新映射到冗余存储器的存储器地址的至少一部分,确定与冗余存储器相关联的可编程元件是否可用于编程,以及当可编程元件 是可用的,编程可编程元件,使得存储器地址将映射到相关联的冗余存储器。

    MEMORY REPAIR SYSTEMS AND METHODS FOR A MEMORY HAVING REDUNDANT MEMORY
    3.
    发明申请
    MEMORY REPAIR SYSTEMS AND METHODS FOR A MEMORY HAVING REDUNDANT MEMORY 有权
    具有冗余存储器的存储器的存储器维修系统和方法

    公开(公告)号:US20110280091A1

    公开(公告)日:2011-11-17

    申请号:US12779597

    申请日:2010-05-13

    IPC分类号: G11C29/00 G11C17/18

    摘要: Memories, memory repair logic, and methods for repairing a memory having redundant memory are disclosed. One such memory includes programmable elements associated with respective redundant memory configured to have memory addresses mapped thereto, the programmable elements configured to be programmed with at least portions of the memory addresses. Such a memory further includes repair logic coupled to the programmable elements and configured to identify programmable elements available for programming to map memory addresses to respective redundant memory. One method for remapping a memory address of a memory to redundant memory includes receiving at least a portion of a memory address to be remapped to redundant memory, determining whether a programmable element associated with the redundant memory is available for programming, and when a programmable element is available, programming the programmable element such that the memory address will be mapped to the associated redundant memory.

    摘要翻译: 公开了用于修复具有冗余存储器的存储器的存储器,存储器修复逻辑和方法。 一个这样的存储器包括与被配置为具有映射到其上的存储器地址的相应冗余存储器相关联的可编程元件,所述可编程元件被配置为用至少部分存储器地址进行编程。 这种存储器还包括耦合到可编程元件的修复逻辑,并且被配置为识别可用于编程以将存储器地址映射到相应冗余存储器的可编程元件。 将存储器的存储器地址重新映射到冗余存储器的一种方法包括:接收要重新映射到冗余存储器的存储器地址的至少一部分,确定与冗余存储器相关联的可编程元件是否可用于编程,以及当可编程元件 是可用的,编程可编程元件,使得存储器地址将映射到相关联的冗余存储器。

    Pseudo fail bit map generation for RAMS during component test and burn-in in a manufacturing environment

    公开(公告)号:US07051253B2

    公开(公告)日:2006-05-23

    申请号:US09931125

    申请日:2001-08-16

    IPC分类号: G11C29/00

    CPC分类号: G11C29/10

    摘要: According to an embodiment of the present invention, a method is provided for determining a fail string for a device. The method includes determining a test pattern for a portion of an address space wherein the test pattern includes at least one address in the address space and the portion of the address space includes at least one x address and at least one y addresses. The method executes a test a plurality of times for each test pattern, wherein every combination of the test pattern is tested, wherein the combinations include each address held at a first potential for at least a first test and a second potential for at least a second test. The method includes determining a fail string for the device including pass/fail results for the test pattern, and combining the pass/fail results in the fail string.

    Memory employing multiple enable/disable modes for redundant elements and testing method using same
    5.
    发明授权
    Memory employing multiple enable/disable modes for redundant elements and testing method using same 失效
    内存采用冗余元件的多个启用/禁用模式和使用相同的测试方法

    公开(公告)号:US06490209B1

    公开(公告)日:2002-12-03

    申请号:US09968749

    申请日:2001-10-02

    IPC分类号: G11C700

    CPC分类号: G11C29/787

    摘要: A memory includes a memory array having a plurality of storage elements; a plurality of replacement storage elements; a plurality of address storage units, each operable to store a replacement address associated with a respective one of the replacement storage elements; a plurality of enable storage units, each operable to store at least first and second enable bits associated with a respective one of the replacement storage elements; and a decode unit operable to (i) activate one of the replacement storage elements when the at least first and second enable bits associated therewith are in an enable state and an input address matches the replacement address associated with the replacement storage element, and (ii) deactivate the replacement storage element when the at least first and second enable bits associated therewith have changed to a disable state.

    摘要翻译: 存储器包括具有多个存储元件的存储器阵列; 多个替换存储元件; 多个地址存储单元,每个地址存储单元可操作以存储与相应一个替换存储元件相关联的替换地址; 多个使能存储单元,每个使能存储单元可操作以存储与所述替换存储元件中的相应一个相关联的至少第一和第二使能位; 以及解码单元,其可操作以(i)当与其相关联的所述至少第一和第二使能位处于使能状态并且输入地址与所述替换存储元件相关联的替换地址匹配时,激活所述替换存储元件中的一个,并且(ii )当与其关联的至少第一和第二使能位已经改变为禁用状态时,停用替换存储元件。

    Memory employing multiple enable/disable modes for redundant elements and testing method using same

    公开(公告)号:US06538939B1

    公开(公告)日:2003-03-25

    申请号:US10197991

    申请日:2002-07-18

    IPC分类号: G11C2900

    CPC分类号: G11C29/787

    摘要: A memory includes a memory array having a plurality of storage elements; a plurality of replacement storage elements; a plurality of address storage units, each operable to store a replacement address associated with a respective one of the replacement storage elements; a plurality of enable storage units, each operable to store at least first and second enable bits associated with a respective one of the replacement storage elements; and a decode unit operable to (i) activate one of the replacement storage elements when the at least first and second enable bits associated therewith are in an enable state and an input address matches the replacement address associated with the replacement storage element, and (ii) deactivate the replacement storage element when the at least first and second enable bits associated therewith have changed to a disable state.