摘要:
A cell placement for an integrated circuit chip is divided into two "chessboard" patterns or "jiggles". Each pattern resembles a chessboard in that it consists of alternating regions of different types or "colors" such that no region of a given color has an edge common with another region of the same color. The jiggles are offset relative to each other such that the regions of one jiggle partially overlap at least two regions of the other jiggle. A placement improvement operation such as simulated annealing is performed sequentially for each color of each jiggle. During each operation, a plurality of parallel processors operate on the regions simultaneously using a previous copy of the entire chip, with one processor being assigned to one or more regions. At the end of each operation, the copy of the chip is updated. The chessboard patterns eliminate unproductive cell moves resulting from adjacent regions having a common edge. The jiggles enable cells to move to their optimal positions from their initial region to any other region on the chip. The regions can have rectangular, triangular or hexagonal shapes.
摘要:
A system for determining an affinity associated with relocating a cell located on a surface of a semiconductor chip to a different location on the surface is disclosed herein. Each cell may be part of a cell net containing multiple cells. The system initially defines a bounding box containing all cells in the net which contains the cell. The system then establishes a penalty vector based on the bounding box and borders of a region containing the cell, computes a normalized sum of penalties for all nets having the cell as a member, and calculates the affinity based on the normalized sum of penalties. Also included in the disclosed system are methods and apparatus for capacity and utilization planning of the use of the floor, or the surface area, and the methods and apparatus for parallelizing the process of affinity based placements using multiple processors. Finally, method and apparatus for connecting the cells based on a Steiner Tree method is disclosed.
摘要:
A cell placement for an integrated circuit chip is divided into two "chessboard" patterns or "jiggles". Each pattern resembles a chessboard in that it consists of alternating regions of different types or "colors" such that no region of a given color has an edge common with another region of the same color. The jiggles are offset relative to each other such that the regions of one jiggle partially overlap at least two regions of the other jiggle. Simulated annealing is performed sequentially for each color of each jiggle. During each operation, a plurality of parallel processors operate on the regions simultaneously using a previous copy of the entire chip, with one processor being assigned to one or more regions. At the end of each operation, the copy of the chip is updated. The chessboard patterns eliminate unproductive cell moves resulting from adjacent regions having a common edge. The jiggles enable cells to move to their optimal positions from their initial region to any other region on the chip. The regions can have rectangular, triangular or hexagonal shapes. An initial temperature for the actual simulated annealing operation is determined by performing simulated annealing without cell swaps with different temperature, and selecting the temperature at which a cost function such as total wirelength does not significantly change.
摘要:
A system for determining an affinity associated with relocating a cell located on a surface of a semiconductor chip to a different location on the surface is disclosed herein. Each cell may be part of a cell net containing multiple cells. The system initially defines a bounding box containing all cells in the net which contains the cell. The system then establishes a penalty vector based on the bounding box and borders of a region containing the cell, computes a normalized sum of penalties for all nets having the cell as a member, and calculates the affinity based on the normalized sum of penalties. Also included in the disclosed system are methods and apparatus for capacity and utilization planning of the use of the floor, or the surface area, and the methods and apparatus for parallelizing the process of affinity based placements using multiple processors. Finally, method and apparatus for connecting the cells based on a Steiner Tree method is disclosed.
摘要:
A system for providing an optimal cluster of cells on the surface of a semiconductor chip is provided herein. The system collects a predetermined quantity of cells, this predetermined quantity containing a center cell, and all cells are assigned a distance value from the center cell. A coordinate is assigned to each cell based on its associated distance value, and new cell positions are calculated based on related cell positions and weights associated with each cell.
摘要:
A system for optimizing placement of a cell on a surface of a semiconductor chip is disclosed herein. The cells may belong to nets and may belong to neighborhoods. The system initially calculates affinities based on repositioning the cell. The system then combines affinities and repositions cells based on these combined affinities. The system then computes a cost function and repeats the combining, repositioning, and computing functions a predetermined number of times.
摘要:
A system for providing an optimal preplacement of cells on a bounded surface of a semiconductor chip is disclosed herein. A percentage of the cells have predetermined interconnections with other cells. The system initially locates the cells on said surface, then computes coordinates for interconnected cells, determines a weight associated with each cell, and calculates a new cell coordinate for each cell based on the coordinates and weights from said determining step.
摘要:
A system for optimally locating cells on the surface of an integrated circuit chip is presented herein. The system comprises constructing a plurality of neighborhoods containing elements positionally related to one another; initially evaluating the lowest level of region hierarchy; iteratively developing a logical one-dimensional preplacement of elements on said surface; performing an affinity driven discrete preplacement optimization; evaluating whether a highest level of regional hierarchy has been attained; iteratively performing a dispersion driven spring system to levelize cell density and an unconstrained sinusoidal optimization; executing a density levelizing procedure; iteratively optimizing while controlling element densities; removing element overlap; iteratively optimizing for desired spacing between elements, adjusting element spacing, and permuting elements; locating elements on grid lines; and iteratively performing a functional sieve crystallization.
摘要:
A system for computing an affinity for relocating a cell on a surface of a semiconductor chip is disclosed herein. The cell is located within a region and belongs to a net of cells. The system initially computes a weight associated with all cells in the net. The sytem then sums the weights of all cells in the net containing the cell for all cells located inside the region and at positions greater than and less than edges of the region and computes the affinity for moving the cell to points on the surface greater than, equal to, and less than the current position of the cell based on the weight sums from said summing function. The computing function further comprises combining the affinities determined based on weight sums with other affinities. The summing function further comprises computing a relationship between the amount of rows and columns of regions on the semiconductor chip surface, and the affinity computation function comprises combining the relationship with the weight sums.
摘要:
A system for optimizing placement of a plurality of cells located on a surface of a semiconductor chip divided into regions by grid lines is disclosed herein. The system first increases the size associated with each cell by a fixed amount. The system then performs various density equalization routines to all cells, and locates cells having a size greater than a predetermined quantity and fixes those cells. Finally, the system executes a plurality of optimal cell movement routines to crystallize cell placement.