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1.发明授权Data processing system and method for reducing cache pollution by write stream memory access patterns 有权用于通过写入流存储器访问模式减少高速缓存污染的数据处理系统和方法公开(公告)号：US08909871B2
公开(公告)日：2014-12-09
申请号：US11462115
申请日：2006-08-03
CPC分类号： G06F12/0888
摘要： A data processing system includes a system memory and a cache hierarchy that caches contents of the system memory. According to one method of data processing, a storage modifying operation having a cacheable target real memory address is received. A determination is made whether or not the storage modifying operation has an associated bypass indication. In response to determining that the storage modifying operation has an associated bypass indication, the cache hierarchy is bypassed, and an update indicated by the storage modifying operation is performed in the system memory. In response to determining that the storage modifying operation does not have an associated bypass indication, the update indicated by the storage modifying operation is performed in the cache hierarchy.
摘要翻译： 数据处理系统包括缓存系统存储器的内容的系统存储器和高速缓存层级。 根据一种数据处理方法，接收具有可缓存目标实际存储器地址的存储修改操作。 确定存储修改操作是否具有相关的旁路指示。 响应于确定存储修改操作具有相关联的旁路指示，忽略高速缓存层级，并且在系统存储器中执行由存储修改操作指示的更新。 响应于确定存储修改操作没有相关联的旁路指示，在高速缓存层级中执行由存储修改操作指示的更新。
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2.发明申请Data Processing System and Method for Reducing Cache Pollution by Write Stream Memory Access Patterns 有权数据处理系统和通过写入流存储器访问模式减少高速缓存污染的方法公开(公告)号：US20080046736A1
公开(公告)日：2008-02-21
申请号：US11462115
申请日：2006-08-03
IPC分类号： H04L9/00
CPC分类号： G06F12/0888
摘要： A data processing system includes a system memory and a cache hierarchy that caches contents of the system memory. According to one method of data processing, a storage modifying operation having a cacheable target real memory address is received. A determination is made whether or not the storage modifying operation has an associated bypass indication. In response to determining that the storage modifying operation has an associated bypass indication, the cache hierarchy is bypassed, and an update indicated by the storage modifying operation is performed in the system memory. In response to determining that the storage modifying operation does not have an associated bypass indication, the update indicated by the storage modifying operation is performed in the cache hierarchy.
摘要翻译： 数据处理系统包括缓存系统存储器的内容的系统存储器和高速缓存层级。 根据一种数据处理方法，接收具有可缓存目标实际存储器地址的存储修改操作。 确定存储修改操作是否具有相关的旁路指示。 响应于确定存储修改操作具有相关联的旁路指示，忽略高速缓存层级，并且在系统存储器中执行由存储修改操作指示的更新。 响应于确定存储修改操作没有相关联的旁路指示，在高速缓存层级中执行由存储修改操作指示的更新。
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公开(公告)号：US08140771B2
公开(公告)日：2012-03-20
申请号：US12024424
申请日：2008-02-01
CPC分类号： G06F12/0822
摘要： In at least one embodiment, a method of data processing in a data processing system having a memory hierarchy includes a processor core executing a storage-modifying memory access instruction to determine a memory address. The processor core transmits to a cache memory within the memory hierarchy a storage-modifying memory access request including the memory address, an indication of a memory access type, and, if present, a partial cache line hint signaling access to less than all granules of a target cache line of data associated with the memory address. In response to the storage-modifying memory access request, the cache memory performs a storage-modifying access to all granules of the target cache line of data if the partial cache line hint is not present and performs a storage-modifying access to less than all granules of the target cache line of data if the partial cache line hint is present.
摘要翻译： 在至少一个实施例中，具有存储器层次的数据处理系统中的数据处理方法包括执行存储修改存储器访问指令以确定存储器地址的处理器核心。 处理器核心向存储器层级内的高速缓冲存储器传送存储修改存储器访问请求，该存储修改存储器访问请求包括存储器地址，存储器访问类型的指示，以及如果存在的话，部分高速缓存行提示信令访问少于所有颗粒的 与存储器地址相关联的数据的目标高速缓存行。 响应于存储修改存储器访问请求，如果不存在部分高速缓存行提示，则高速缓存存储器对目标高速缓存行数据行的所有颗粒进行存储修改访问，并执行对小于全部的存储修改访问 如果存在部分高速缓存线提示，则目标高速缓存行数据的颗粒。
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4.发明授权公开(公告)号：US08332588B2
公开(公告)日：2012-12-11
申请号：US13349315
申请日：2012-01-12
IPC分类号： G06F12/04
CPC分类号： G06F12/0822
摘要： Analyzing pre-processed code includes identifying at least one storage-modifying construct specifying a storage-modifying memory access to a memory hierarchy of a data processing system and determining if more than one granule of a cache line of data containing multiple granules that is targeted by the storage-modifying construct is subsequently referenced by said pre-processed code. Post-processed code including a storage-modifying instruction corresponding to the at least one storage-modifying construct in the pre-processed code is generated and stored. Generating the post-processed code includes marking the storage-modifying instruction with a partial cache line hint indicating that said storage-modifying instruction targets less than a full cache line of data within a memory hierarchy if the analyzing indicates only one granule of the target cache line will be accessed while the cache line is held in the cache memory and otherwise refraining from marking the storage-modifying instruction with the partial cache line hint.
摘要翻译： 分析预处理的代码包括识别指定对数据处理系统的存储器层次结构的存储修改存储器访问的至少一个存储修改结构，并且确定是否存在多个颗粒的高速缓存行数据，所述数据包含多个颗粒的高速缓存行是由 存储修改结构随后由所述预处理代码引用。 生成并存储包括与预处理代码中的至少一个存储修改结构对应的存储修改指令的后处理代码。 生成后处理代码包括用部分高速缓存线提示标记存储修改指令，指示所述存储修改指令的目标小于存储器层次结构内的完整高速缓存数据行，如果分析仅指示目标高速缓存的一个颗粒 将高速缓存线保持在高速缓存存储器中，并以其它方式避免使用部分高速缓存线提示来标记存储修改指令。
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5.发明申请PERFORMING A PARTIAL CACHE LINE STORAGE-MODIFYING OPERATION BASED UPON A HINT 失效根据提示执行部分缓存线存储 - 修改操作公开(公告)号：US20120265938A1
公开(公告)日：2012-10-18
申请号：US13349315
申请日：2012-01-12
IPC分类号： G06F12/08
CPC分类号： G06F12/0822
摘要： Analyzing pre-processed code includes identifying at least one storage-modifying construct specifying a storage-modifying memory access to a memory hierarchy of a data processing system and determining if more than one granule of a cache line of data containing multiple granules that is targeted by the storage-modifying construct is subsequently referenced by said pre-processed code. Post-processed code including a storage-modifying instruction corresponding to the at least one storage-modifying construct in the pre-processed code is generated and stored. Generating the post-processed code includes marking the storage-modifying instruction with a partial cache line hint indicating that said storage-modifying instruction targets less than a full cache line of data within a memory hierarchy if the analyzing indicates only one granule of the target cache line will be accessed while the cache line is held in the cache memory and otherwise refraining from marking the storage-modifying instruction with the partial cache line hint.
摘要翻译： 分析预处理的代码包括识别指定对数据处理系统的存储器层次结构的存储修改存储器访问的至少一个存储修改结构，并且确定是否存在多个颗粒的高速缓存行数据，所述数据包含多个颗粒的高速缓存行是由 存储修改结构随后由所述预处理代码引用。 生成并存储包括与预处理代码中的至少一个存储修改结构对应的存储修改指令的后处理代码。 生成后处理代码包括用部分高速缓存线提示标记存储修改指令，指示所述存储修改指令的目标小于存储器层次结构内的完整高速缓存数据行，如果分析仅指示目标高速缓存的一个颗粒 将高速缓存线保持在高速缓存存储器中，并以其它方式避免使用部分高速缓存线提示来标记存储修改指令。
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6.发明授权Processor, data processing system, and method for initializing a memory block in a data processing system having multiple coherency domains 有权处理器，数据处理系统和用于初始化具有多个相干域的数据处理系统中的存储器块的方法公开(公告)号：US07475196B2
公开(公告)日：2009-01-06
申请号：US11388001
申请日：2006-03-23
IPC分类号： G06F13/00
CPC分类号： G06F12/0822 , G06F12/084
摘要： A data processing system includes at least first and second coherency domains, each including at least one processor core and a memory. In response to an initialization operation by a processor core that indicates a target memory block to be initialized, a cache memory in the first coherency domain determines a coherency state of the target memory block with respect to the cache memory. In response to the determination, the cache memory selects a scope of broadcast of an initialization request identifying the target memory block. A narrower scope including the first coherency domain and excluding the second coherency domain is selected in response to a determination of a first coherency state, and a broader scope including the first coherency domain and the second coherency domain is selected in response to a determination of a second coherency state. The cache memory then broadcasts an initialization request with the selected scope. In response to the initialization request, the target memory block is initialized within a memory of the data processing system to an initialization value.
摘要翻译： 数据处理系统至少包括第一和第二相干域，每个域包括至少一个处理器核和存储器。 响应于指示要初始化的目标存储器块的处理器核心的初始化操作，第一相干域中的高速缓冲存储器确定目标存储器块相对于高速缓存存储器的一致性状态。 响应于该确定，高速缓存存储器选择识别目标存储器块的初始化请求的广播范围。 响应于第一相关性状态的确定而选择包括第一相关域并且排除第二相关性域的较窄范围，并且响应于确定第一相关性域的第一相关性域和第二相关域 第二一致性状态。 然后，高速缓冲存储器播放具有所选范围的初始化请求。 响应于初始化请求，将目标存储器块在数据处理系统的存储器内初始化为初始化值。
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公开(公告)号：US08095733B2
公开(公告)日：2012-01-10
申请号：US12419343
申请日：2009-04-07
CPC分类号： G06F12/0811 , G06F9/30101 , G06F9/3851 , G06F9/522
摘要： A data processing system includes an interconnect fabric, a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs), and a plurality of processing units coupled to the interconnect fabric and operable to access the virtual barrier synchronization region. Each of the plurality of processing units includes a processor core and a cache memory including a cache controller and a cache array that caches VBSR lines from the virtual barrier synchronization region of the system memory. The cache controller of a first processing unit, responsive to a memory access request from its processor core that targets a first VBSR line, transfers responsibility for writing back to the virtual barrier synchronization region a second VBSR line contemporaneously held in the cache arrays of first, second and third processing units. The responsibility is transferred via an election held over the interconnect fabric.
摘要翻译： 数据处理系统包括互连结构，耦合到互连结构并包括分配给虚拟屏障同步寄存器（VBSR）的存储的虚拟屏障同步区域的系统存储器，以及耦合到互连结构的多个处理单元， 访问虚拟屏障同步区域。 多个处理单元中的每一个包括处理器核心和高速缓存存储器，其包括高速缓存控制器和从系统存储器的虚拟屏障同步区域缓存VBSR行的高速缓存阵列。 响应于来自其处理器核心的第一VBSR线路的存储器访问请求的第一处理单元的高速缓存控制器将负责向第一虚拟屏障同步区域写回同时保存在第一VBSR线路的高速缓存阵列中的第二VBSR线路， 第二和第三处理单元。 通过互连结构上的选举来转移责任。
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公开(公告)号：US20100257316A1
公开(公告)日：2010-10-07
申请号：US12419343
申请日：2009-04-07
CPC分类号： G06F12/0811 , G06F9/30101 , G06F9/3851 , G06F9/522
摘要： A data processing system includes an interconnect fabric, a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs), and a plurality of processing units coupled to the interconnect fabric and operable to access the virtual barrier synchronization region. Each of the plurality of processing units includes a processor core and a cache memory including a cache controller and a cache array that caches VBSR lines from the virtual barrier synchronization region of the system memory. The cache controller of a first processing unit, responsive to a memory access request from its processor core that targets a first VBSR line, transfers responsibility for writing back to the virtual barrier synchronization region a second VBSR line contemporaneously held in the cache arrays of first, second and third processing units. The responsibility is transferred via an election held over the interconnect fabric.
摘要翻译： 数据处理系统包括互连结构，耦合到互连结构并包括分配给虚拟屏障同步寄存器（VBSR）的存储的虚拟屏障同步区域的系统存储器，以及耦合到互连结构的多个处理单元， 访问虚拟屏障同步区域。 多个处理单元中的每一个包括处理器核心和高速缓存存储器，其包括高速缓存控制器和从系统存储器的虚拟屏障同步区域缓存VBSR行的高速缓存阵列。 响应于来自其处理器核心的第一VBSR线路的存储器访问请求的第一处理单元的高速缓存控制器将负责向第一虚拟屏障同步区域写回同时保存在第一VBSR线路的高速缓存阵列中的第二VBSR线路， 第二和第三处理单元。 通过互连结构上的选举来转移责任。
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公开(公告)号：US08131935B2
公开(公告)日：2012-03-06
申请号：US12419364
申请日：2009-04-07
CPC分类号： G06F12/0811 , G06F9/522
摘要： A data processing system includes an interconnect fabric, a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs), and a plurality of processing units coupled to the interconnect fabric and operable to access the virtual barrier synchronization region of the system memory. Each of the plurality of processing units includes a processor core and a cache memory including a cache array that caches VBSR lines from the virtual barrier synchronization region of the system memory and a cache controller. The cache controller, responsive to a store request from the processor core to update a particular VBSR line, performs a non-blocking update of the cache array in each other of the plurality of processing units contemporaneously holding a copy of the particular VBSR line by transmitting a VBSR update command on the interconnect fabric.
摘要翻译： 数据处理系统包括互连结构，耦合到互连结构并包括分配给虚拟屏障同步寄存器（VBSR）的存储的虚拟屏障同步区域的系统存储器，以及耦合到互连结构的多个处理单元， 访问系统内存的虚拟屏障同步区域。 多个处理单元中的每一个包括处理器核心和高速缓存存储器，其包括从系统存储器的虚拟屏障同步区域缓存VBSR行的缓存阵列和高速缓存控制器。 高速缓存控制器响应于来自处理器核心的存储请求来更新特定VBSR线路，通过发送来同时保存特定VBSR线路的副本的多个处理单元中的彼此之间的高速缓存阵列的非阻塞更新 互连结构上的VBSR更新命令。
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10.发明授权Processor, data processing system, and method for initializing a memory block to an initialization value without a cache first obtaining a data valid copy 失效处理器，数据处理系统和用于将存储器块初始化为初始化值的方法，而没有高速缓存首先获得数据有效副本公开(公告)号：US07290094B2
公开(公告)日：2007-10-30
申请号：US11130907
申请日：2005-05-17
IPC分类号： G06F13/00
CPC分类号： G06F12/0831
摘要： In response to receiving an initialization operation from an associated processor core that indicates a target memory block to be initialized, a cache memory determines a coherency state of the target memory block. In response to a determination that the target memory block has a data-invalid coherency state with respect to the cache memory, the cache memory issues on a interconnect a corresponding initialization request indicating the target memory block. In response to the initialization request, the target memory block is initialized within a memory of the data processing system to an initialization value. The target memory block may thus be initialized without the cache memory holding a valid copy of the target memory block.
摘要翻译： 响应于从指示要初始化的目标存储器块的相关联的处理器核心接收到初始化操作，高速缓存存储器确定目标存储器块的一致性状态。 响应于目标存储器块相对于高速缓冲存储器具有数据无效一致性状态的确定，高速缓冲存储器在互连上发出指示目标存储器块的对应的初始化请求。 响应于初始化请求，将目标存储器块在数据处理系统的存储器内初始化为初始化值。 因此，可以初始化目标存储器块，而不使高速缓冲存储器保持目标存储器块的有效副本。
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