公开(公告)号：US08549454B1

公开(公告)日：2013-10-01

申请号：US13554418

申请日：2012-07-20

申请人： Raymond Kong ,  David A. Knol ,  Frederic Revenu ,  Dinesh K. Monga

发明人： Raymond Kong ,  David A. Knol ,  Frederic Revenu ,  Dinesh K. Monga

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/06

摘要： In one embodiment, a method for propagating design constraints between a module and a module instance in a circuit design is provided. A port of the module and a port/pin of the circuit design are determined, between which constraints are to be propagated. The determination of the port/pin includes determining whether or not pin of the module instance corresponding to the port is directly connected to a top-level port of the circuit design. In response to determining that the pin is directly connected to a top-level port, the top-level port is selected as the port/pin. In response to determining that the pin is not directly connected to the top-level port, the pin is selected as the port/pin. Design constraints are propagated between the port and the selected port/pin. The propagated design constraints are stored in a storage device.

摘要翻译： 在一个实施例中，提供了一种用于在电路设计中在模块和模块实例之间传播设计约束的方法。 确定模块的端口和电路设计的端口/引脚，在这些约束之间进行传播。 端口/引脚的确定包括确定对应于端口的模块实例的引脚是否直接连接到电路设计的顶级端口。 响应于确定引脚直接连接到顶级端口，顶级端口被选择为端口/引脚。 响应于确定引脚不直接连接到顶级端口，该引脚被选择为端口/引脚。 设计约束在端口和选定端口/引脚之间传播。 传播的设计约束存储在存储设备中。