公开(公告)号：US12211570B2

公开(公告)日：2025-01-28

申请号：US18129087

申请日：2023-03-31

Applicant: Realtek Semiconductor Corp.

Inventor： Li-Wei Deng ,  Ying-Yen Chen ,  Chih-Tung Chen

IPC: G11C29/00 ,  G11C7/10 ,  G11C29/10 ,  G11C29/12

Abstract: A test circuit coupled to a memory device and configured to read data stored in the memory device during a memory dump, includes a dump controller and a pattern generator. The dump controller triggers the pattern generator to start a pattern generating operation in response to a setting of memory dump mode by a processor. The pattern generator generates multiple control signals in the pattern generating operation and provides the control signals to the memory device. The control signals include an address signal, a memory enable signal and a read enable signal. The address signal includes multiple memory addresses arranged in multiple consecutive clock cycles of the processor. The consecutive clock cycles of the processor is provided to read the data stored in the memory addresses.

公开(公告)号：US20230335208A1

公开(公告)日：2023-10-19

申请号：US18129087

申请日：2023-03-31

Applicant: Realtek Semiconductor Corp.

Inventor： Li-Wei Deng ,  Ying-Yen Chen ,  Chih-Tung Chen

IPC: G11C29/10 ,  G11C29/12 ,  G11C7/10

CPC classification number: G11C29/10 ,  G11C29/12015 ,  G11C7/1069

Abstract: A test circuit coupled to a memory device and configured to read data stored in the memory device during a memory dump, includes a dump controller and a pattern generator. The dump controller triggers the pattern generator to start a pattern generating operation in response to a setting of memory dump mode by a processor. The pattern generator generates multiple control signals in the pattern generating operation and provides the control signals to the memory device. The control signals include an address signal, a memory enable signal and a read enable signal. The address signal includes multiple memory addresses arranged in multiple consecutive clock cycles of the processor. The consecutive clock cycles of the processor is provided to read the data stored in the memory addresses.