公开(公告)号：US12141869B2

公开(公告)日：2024-11-12

申请号：US18495650

申请日：2023-10-26

Applicant: REBELLIONS INC.

Inventor： Hyunsung Kim ,  Sungyeob Yoo ,  Jinwook Oh

IPC: G06Q40/04

Abstract: A method for high frequency trading is provided, which is performed by one or more processors, and includes calculating a latency for a market order for each of a plurality of candidate batch sizes, selecting a batch size from among the plurality of candidate batch sizes based on the calculated latency, generating input data corresponding to the selected batch size using market data for a target item, using a machine learning model, generating prediction data for the target item at a future time point associated with the selected batch size, based on the generated input data, and generating order data for the target item based on the generated prediction data.

公开(公告)号：US20240320037A1

公开(公告)日：2024-09-26

申请号：US18674752

申请日：2024-05-24

Applicant: Rebellions Inc.

Inventor： Wongyu Shin ,  Miock Chi ,  Hongyun Kim ,  Jinwook Oh ,  Juyeong Yoon

IPC: G06F9/48 ,  G06F9/38

CPC classification number: G06F9/4881 ,  G06F9/3838

Abstract: A neural processing device and a method for managing tasks thereof are provided. The neural processing device includes a neural core configured to perform a task and generate a completion signal for completion of the task, a core global configured to transfer task information for the task to the neural core and receive the completion signal of the task from the neural core, and a task manager configured to generate and transmit the task information to the core global, receive the completion signal from the core global, generate a completion report, and transmit the completion report.

公开(公告)号：US11954488B2

公开(公告)日：2024-04-09

申请号：US18459241

申请日：2023-08-31

Applicant: Rebellions Inc.

Inventor： Karim Charfi ,  Jinwook Oh

IPC: G06F9/30

CPC classification number: G06F9/30025 ,  G06F9/3001 ,  G06F9/30098

Abstract: A neural processing device, a processing element included therein and a method for operating various formats of the neural processing device are provided. The neural processing device includes at least one neural processor, a shared memory shared by the at least one neural processor, and a global interconnection configured to transmit data between the at least one neural processor and the shared memory, wherein each of the at least one neural processor comprises at least one processing element, each of the at least one processing element receives an input in a first format and thereby performs an operation, and receives an input in a second format that is different from the first format and thereby performs an operation if a format conversion signal is received, and the first format and the second format have a same number of bits.

公开(公告)号：US11934942B2

公开(公告)日：2024-03-19

申请号：US18184543

申请日：2023-03-15

Applicant: Rebellions Inc.

Inventor： Jinwook Oh

IPC: G06N3/06 ,  G06F9/50 ,  G06F13/14 ,  G06N3/063

CPC classification number: G06N3/063 ,  G06F9/5011 ,  G06F13/14 ,  G06F2209/501 ,  G06F2209/508

Abstract: A neural processing device comprising processing circuitry are provided. A neural processing device comprises a plurality of processing engine groups; a first memory shared by the plurality of engine groups; a first interconnection configured to transmit data between the first memory and the plurality of processing engine groups. The neural processing device is configured to provide hardware resource to the plurality of processing engine groups. The at least one of the plurality of processing engine groups comprises a plurality of processing engines, each of the plurality of processing engines comprising an array of a plurality of processing elements interconnected by a mesh style network, the processing elements being reconfigurable; a second memory shared by the plurality of processing engines; and a second interconnection configured to transmit data between the second memory and the plurality of processing engines.

公开(公告)号：US20240086150A1

公开(公告)日：2024-03-14

申请号：US18511942

申请日：2023-11-16

Applicant: Rebellions Inc.

Inventor： Jaewan Bae ,  Jinwook Oh ,  Karim Charfi

IPC: G06F7/533 ,  G06F7/50 ,  G06F7/535 ,  G06F7/544 ,  G06N3/063

CPC classification number: G06F7/533 ,  G06F7/50 ,  G06F7/535 ,  G06F7/5443 ,  G06N3/063

Abstract: The present disclosure discloses a processing element and a neural processing device including the processing element. The processing element includes a weight register configured to store a weight, an input activation register configured to store input activation, a flexible multiplier configured to generate result data by performing a multiplication operation of the weight and the input activation by using a first multiplier of a first precision or using both the first multiplier and a second multiplier of the first precision in response to a calculation mode signal and a saturating adder configured to generate a partial sum by using the result data.

公开(公告)号：US20240078110A1

公开(公告)日：2024-03-07

申请号：US18459241

申请日：2023-08-31

Applicant: Rebellions Inc.

Inventor： Karim Charfi ,  Jinwook Oh

IPC: G06F9/30

CPC classification number: G06F9/30025 ,  G06F9/3001 ,  G06F9/30098

Abstract: A neural processing device, a processing element included therein and a method for operating various formats of the neural processing device are provided. The neural processing device includes at least one neural processor, a shared memory shared by the at least one neural processor, and a global interconnection configured to transmit data between the at least one neural processor and the shared memory, wherein each of the at least one neural processor comprises at least one processing element, each of the at least one processing element receives an input in a first format and thereby performs an operation, and receives an input in a second format that is different from the first format and thereby performs an operation if a format conversion signal is received, and the first format and the second format have a same number of bits.

公开(公告)号：US20220300816A1

公开(公告)日：2022-09-22

申请号：US17655348

申请日：2022-03-17

Applicant: Rebellions Inc.

Inventor： Jinwook Oh

IPC: G06N3/08 ,  G06N3/063 ,  G06F9/38 ,  G06F9/30

Abstract: A neural processing device and method for pruning thereof are provided. The neural processing device includes a processing unit configured to perform calculations, an L0 memory configured to store input and output data of the processing unit, wherein the input and output data include a two-dimensional weight matrix and a weight manipulator configured to receive the two-dimensional weight matrix and partition it into preset sizes to thereby generate partitioned matrices, to generate a pruning matrix by pruning the partitioned matrix, and to transmit the pruning matrix to the processing unit.

公开(公告)号：US12236209B2

公开(公告)日：2025-02-25

申请号：US18511942

申请日：2023-11-16

Applicant: Rebellions Inc.

Inventor： Jaewan Bae ,  Jinwook Oh ,  Karim Charfi

IPC: G06F7/533 ,  G06F7/544

Abstract: The present disclosure discloses a processing element and a neural processing device including the processing element. The processing element includes a weight register configured to store a weight, an input activation register configured to store input activation, a flexible multiplier configured to generate result data by performing a multiplication operation of the weight and the input activation by using a first multiplier of a first precision or using both the first multiplier and a second multiplier of the first precision in response to a calculation mode signal and a saturating adder configured to generate a partial sum by using the result data.

公开(公告)号：US20240273348A1

公开(公告)日：2024-08-15

申请号：US18642434

申请日：2024-04-22

Applicant: Rebellions Inc.

Inventor： Jinwook Oh

IPC: G06N3/063 ,  G06F9/50 ,  G06F13/14

CPC classification number: G06N3/063 ,  G06F9/5011 ,  G06F13/14 ,  G06F2209/501 ,  G06F2209/508

Abstract: A neural processing device processing circuitry comprising and method for controlling the same are provided. The neural processing device comprises at least one processing engine group each of which includes at least one processing engines, a first memory shared by the at least one processing engine group, and an interconnection configured to exchange data between the at least one processing engine group and the first memory. The processing circuitry is configured to monitor the at least one processing engine to check performance related to the at least one processing engine, and provide hardware resources to at least one of the first memory, the interconnection or the at least one processing engine, according to the performance.

公开(公告)号：US20240185045A1

公开(公告)日：2024-06-06

申请号：US18441958

申请日：2024-02-14

Applicant: Rebellions Inc.

Inventor： Jinwook Oh

IPC: G06N3/063 ,  G06F9/50 ,  G06F13/14

CPC classification number: G06N3/063 ,  G06F9/5011 ,  G06F13/14 ,  G06F2209/501 ,  G06F2209/508

Abstract: A neural processing device comprising processing circuitry are provided. A neural processing device comprises a plurality of processing engine groups; a first memory shared by the plurality of engine groups; a first interconnection configured to transmit data between the first memory and the plurality of processing engine groups. The neural processing device is configured to provide hardware resource to the plurality of processing engine groups. The at least one of the plurality of processing engine groups comprises a plurality of processing engines, each of the plurality of processing engines comprising an array of a plurality of processing elements interconnected by a mesh style network, the processing elements being reconfigurable; a second memory shared by the plurality of processing engines; and a second interconnection configured to transmit data between the second memory and the plurality of processing engines.