公开(公告)号：US11271710B1

公开(公告)日：2022-03-08

申请号：US17106483

申请日：2020-11-30

Applicant: Renesas Electronics America Inc.

Inventor： Ilhyun Cho ,  Kwang-Seok Han ,  Soonseob Lee ,  Heewon Suh ,  Gilpyo Lee

IPC: H04L7/00 ,  H03K3/012 ,  H03B27/00 ,  H03H7/21

Abstract: A quadrature phase clock generator includes a tunable polyphase filter and a phase detector. The tunable polyphase filter is configured to receive an input clock signal and generate four quadrature phase clock signals. The phase detector is coupled to receive at least two of the four quadrature phase clock signals and generate a control signal adapted to tune the polyphase filter based on the received quadrature phase clock signals. Further, the phase detector is configured to provide the control signal to the polyphase filter in a feedback loop. Based on the control signal from the phase detector, the tunable polyphase filter generates four tuned quadrature phase clock signals as output phase clock signals.