公开(公告)号：US20200328157A1

公开(公告)日：2020-10-15

申请号：US16911852

申请日：2020-06-25

Applicant: Renesas Electronics Corporation

Inventor： Yoshinori DEGUCHI ,  Akinobu WATANABE

IPC: H01L23/535 ,  H01L21/3205 ,  H01L23/522 ,  H01L21/768 ,  H01L21/66 ,  H01L23/538 ,  H01L23/00 ,  H01L23/58

Abstract: A semiconductor device includes a semiconductor substrate SB and a wiring structure formed on a main surface of the semiconductor substrate SB. The uppermost first wiring layer among a plurality of wiring layers included in the wiring structure includes a pad PD, and the pad PD has a first region for bonding a copper wire and a second region for bringing a probe into contact with the pad. A second wiring layer that is lower by one layer than the first wiring layer among the plurality of wiring layers included in the wiring structure includes a wiring line M6 arranged immediately below the pad PD, the wiring line M6 is arranged immediately below a region other than the first region of the pad PD, and no conductor pattern in the same layer as a layer of the wiring line M6 belong is formed immediately below the first region of the pad PD.

公开(公告)号：US20180374795A1

公开(公告)日：2018-12-27

申请号：US15774664

申请日：2016-02-23

Applicant: Renesas Electronics Corporation

Inventor： Yoshinori DEGUCHI ,  Akinobu WATANABE

IPC: H01L23/535 ,  H01L23/522 ,  H01L23/00 ,  H01L23/58 ,  H01L23/538 ,  H01L21/66

Abstract: A semiconductor device includes a semiconductor substrate SB and a wiring structure formed on a main surface of the semiconductor substrate SB. The uppermost first wiring layer among a plurality of wiring layers included in the wiring structure includes a pad PD, and the pad PD has a first region for bonding a copper wire and a second region for bringing a probe into contact with the pad. A second wiring layer that is lower by one layer than the first wiring layer among the plurality of wiring layers included in the wiring structure includes a wiring line M6 arranged immediately below the pad PD, the wiring line M6 is arranged immediately below a region other than the first region of the pad PD, and no conductor pattern in the same layer as a layer of the wiring line M6 belong is formed immediately below the first region of the pad PD.