公开(公告)号：US20160274184A1

公开(公告)日：2016-09-22

申请号：US14964362

申请日：2015-12-09

申请人： Renesas Electronics Corporation

发明人： Hiroyuki IWATA

IPC分类号： G01R31/3177 ,  G06F17/50

CPC分类号： G06F17/5045 ,  G01R31/318563 ,  G01R31/318566

摘要： In a compression scan, the number of test steps is reduced without reducing a defection efficiency. A semiconductor apparatus includes one or more scan chains each including one or more MMSFFs being serially connected and combinational circuits and can switch between a scan shift operation and a capture operation. The MMSFF includes an MUX that selects one of an external input test signal which is externally input and a shift test signal which is input via the MMSFF in a preceding stage in the same scan chain, and an FF that outputs one of the external input test signal and the shift test signal which has been selected by the MUX.

摘要翻译： 在压缩扫描中，测试步骤的数量减少，而不会降低缺陷效率。 半导体装置包括一个或多个扫描链，每个扫描链包括串联连接的一个或多个MMSFF和组合电路，并且可以在扫描移位操作和捕获操作之间切换。 MMSFF包括选择外部输入的外部输入测试信号和在同一扫描链中的前一级经由MMSFF输入的移位测试信号的MUX，以及输出外部输入测试之一的FF 信号和由MUX选择的移位测试信号。

公开(公告)号：US20170089979A1

公开(公告)日：2017-03-30

申请号：US15220427

申请日：2016-07-27

申请人： Renesas Electronics Corporation

发明人： Hiroyuki IWATA ,  Jun MATSUSHIMA

IPC分类号： G01R31/3177 ,  G01R31/317

CPC分类号： G01R31/3177 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/31813 ,  G01R31/3183 ,  G01R31/318536 ,  G01R31/318583

摘要： It is possible to reduce the number of test point circuits to be inserted necessary to accomplish a target fault coverage, to suppress an increase in an area overhead, and to reduce a test time. A test point circuit according to an embodiment constitutes a scan chain, and captures, in one capture operation period of a clock sequential test, a first operation result in a second capture clock that comes after a first capture clock, the first operation result having been captured by a test point circuit at a previous stage or a last stage of the scan chain in the first capture clock.