公开(公告)号：US09543315B1

公开(公告)日：2017-01-10

申请号：US15212331

申请日：2016-07-18

Applicant: Renesas Electronics Corporation

Inventor： Hiraku Chakihara ,  Satoshi Abe

IPC: H01L29/78 ,  H01L27/115 ,  H01L49/02

CPC classification number: H01L27/11573 ,  H01L27/0629 ,  H01L28/90 ,  H01L29/66181 ,  H01L29/7833

Abstract: The memory cell includes a gate insulating film, a control gate electrode, a cap insulating film, a cap layer, another gate insulating film, and a memory gate electrode. A laminated capacitive element includes a capacitive electrode which is constituted by a sub-electrode and another sub-electrode formed of mesa portions (protruding portions) disposed on the sub-electrode at a predetermined interval and each having an upper surface and side surfaces, a capacitive insulating film which is formed along an upper surface of the sub-electrode and the upper surface and the side surfaces of the another sub-electrode, and another capacitive electrode which is formed on the capacitive insulating film. Further, the control gate electrode and the sub-electrode are made of a conductor film, the cap layer and the another sub-electrode are made of other conductor film, and the memory gate electrode and the another capacitive electrode are made of another conductor film.

Abstract translation: 存储单元包括栅极绝缘膜，控制栅电极，帽绝缘膜，盖层，另一栅极绝缘膜和存储栅电极。 叠层电容元件包括由副电极构成的电容电极和以预定间隔设置在副电极上的台面部（突出部）形成的各自具有上表面和侧面的另一副电极， 沿着副电极的上表面和另一子电极的上表面和侧表面形成的电容绝缘膜和形成在电容绝缘膜上的另一电容电极。 此外，控制栅电极和副电极由导体膜制成，盖层和另一副电极由其他导体膜制成，并且存储栅电极和另一电容电极由另一导体膜 。

公开(公告)号：US20160260795A1

公开(公告)日：2016-09-08

申请号：US14992067

申请日：2016-01-11

Applicant: Renesas Electronics Corporation

Inventor： Satoshi Abe ,  Hiraku Chakihara ,  Kyoko Umeda ,  Yoshiyuki Kawashima ,  Kentaro Saito

IPC: H01L49/02 ,  H01L27/115

CPC classification number: H01L28/60 ,  H01L27/0629 ,  H01L27/11573

Abstract: In a semiconductor device including a nonvolatile memory, a novel stacked capacitive element is provided. The semiconductor device includes the stacked capacitive element including a first capacitive electrode made of an n-type well region formed in a semiconductor substrate, a second capacitive electrode formed so as to overlap the first capacitive electrode via a first capacitive insulating film, a third capacitive electrode formed so as to overlap the second capacitive electrode via a second capacitive insulating film, and a fourth capacitive electrode formed so as to overlap the third capacitive electrode via a third capacitive insulating film. To the first and third capacitive electrodes, a first potential is applied and, to the second and fourth capacitive electrodes, a second potential different from the first potential is applied.

Abstract translation: 在包括非易失性存储器的半导体器件中，提供了一种新颖的叠层电容元件。 半导体器件包括堆叠的电容元件，其包括由形成在半导体衬底中的n型阱区域构成的第一电容电极，经由第一电容绝缘膜形成为与第一电容电极重叠的第二电容电极，第三电容 电极，其经由第二电容绝缘膜与第二电容电极重叠形成，第四电容电极通过第三电容绝缘膜与第三电容电极重叠形成。 对于第一和第三电容电极，施加第一电位，并且向第二和第四电容电极施加不同于第一电位的第二电位。