公开(公告)号：US20160218060A1

公开(公告)日：2016-07-28

申请号：US14994263

申请日：2016-01-13

Applicant: Renesas Electronics Corporation

Inventor： Yoshihisa MATSUBARA ,  Takashi ISHIGAMI

IPC: H01L23/528 ,  H01L23/532 ,  H01L29/49 ,  H01L27/088 ,  H01L29/66

Abstract: An improvement is achieved in the performance of a semiconductor-device. The semiconductor device includes MISFETs formed in the upper surface of a substrate, a plurality of wiring layers stacked over the upper surface of the substrate, and a plurality of plugs each coupling two of the wiring layers to each other. The wiring layers located under the uppermost wiring layer include wires. The uppermost wiring layer includes a pad, an insulating film formed over the pad, and an opening extending through the insulating film and reaching the pad. The MISFETs and the wires overlap the opening in plan view. None of the plurality of plugs overlaps the opening in plan view.

Abstract translation: 半导体器件的性能得到改善。 半导体器件包括形成在衬底的上表面中的MISFET，在衬底的上表面上堆叠的多个布线层，以及将两个布线层彼此耦合的多个插塞。 位于最上层布线层下方的布线层包括导线。 最上面的布线层包括衬垫，形成在衬垫上的绝缘膜，以及延伸穿过绝缘膜并到达衬垫的开口。 MISFET和电线在平面图中与开口重叠。 多个插头中的任一个在平面图中与开口重叠。