公开(公告)号：US20180080984A1

公开(公告)日：2018-03-22

申请号：US15800936

申请日：2017-11-01

Applicant: Renesas Electronics Corporation

Inventor： Yukitoshi TSUBOI ,  Hideo NAGANO ,  Hiroshi NAGAOKA ,  Yusuke MATSUNAGA ,  Yutaka IGAKU ,  Naotaka KUBOTA

IPC: G01R31/3177 ,  G06F11/08 ,  G01R31/3185

Abstract: A semiconductor device includes a system bus, a plurality of Central Processing Unit (CPU) cores each connected to the system bus, including a scan chain, and being assigned one or more tasks and configured to perform one of the tasks in a normal operation state, and a diagnostic test circuit connected to the system bus and capable of communicating with the plurality of the CPU cores, and configured to perform a scan test for the plurality of the CPU cores by using the scan chain. The plurality of the CPU cores outputs a test start instruction signal to the diagnostic test circuit, when the test start instruction signal is output from one of the plurality of the CPU cores, the diagnostic test circuit performs a scan test for the one of the plurality of the CPU cores in accordance with the test start instruction signal.

公开(公告)号：US20150293173A1

公开(公告)日：2015-10-15

申请号：US14676743

申请日：2015-04-01

Applicant: Renesas Electronics Corporation

Inventor： Yukitoshi TSUBOI ,  Hideo NAGANO ,  Hiroshi NAGAOKA ,  Yusuke MATSUNAGA ,  Yutaka IGAKU ,  Naotaka KUBOTA

IPC: G01R31/3177 ,  G06F11/08

CPC classification number: G01R31/3177 ,  G01R31/318544 ,  G06F11/08

Abstract: Deterioration in operation performance due to a fault diagnosis is prevented. A semiconductor device 90 according to the present invention includes a plurality of CPU cores 91 to 94 each including a scan chain, and a diagnostic test circuit 95 that performs a scan test for the plurality of CPU cores 91 to 94 by using the scan chain of the CPU core. The diagnostic test circuit 95 performs a scan test for each of the plurality of CPU cores 91 to 94 in a predetermined order on a periodic basis so that execution time periods of the scan tests do not overlap each other.

Abstract translation: 防止由故障诊断引起的操作性能恶化。 根据本发明的半导体器件90包括多个包含扫描链的CPU核91至94，以及诊断测试电路95，其通过使用扫描链进行多个CPU核91至94的扫描测试 CPU内核。 诊断测试电路95以周期性的预定顺序对多个CPU核心91至94中的每一个执行扫描测试，使得扫描测试的执行时间周期彼此不重叠。