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1.发明授权System having a controller device, a buffer device and a plurality of memory devices 失效具有控制器装置，缓冲装置和多个存储装置的系统公开(公告)号：US07320047B2
公开(公告)日：2008-01-15
申请号：US11136995
申请日：2005-05-25
IPC分类号： G06F12/00
CPC分类号： G11C29/028 , G06F13/1673 , G06F13/1684 , G11C5/04 , G11C7/10 , G11C29/02 , G11C29/50012
摘要： A system comprises a controller device, an integrated circuit buffer device and a first and second memory device. A first plurality of signal lines is coupled to the controller device. A second plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The second plurality of signal lines carries first address information from the integrated circuit buffer device to the first memory device. A third plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The third plurality of signal lines carries first control information from the integrated circuit buffer device to the first memory device. A first signal line is coupled to the first memory device and the integrated circuit buffer device. The first signal line carries a first signal from the integrated circuit buffer device to the first memory device. The first signal synchronizes communication of the first control information from the integrated circuit buffer device to the first memory device.
摘要翻译： 一种系统包括控制器装置，集成电路缓冲装置以及第一和第二存储装置。 第一多个信号线耦合到控制器设备。 第二多个信号线耦合到第一存储器件和集成电路缓冲器件。 第二多个信号线将第一地址信息从集成电路缓冲器装置传送到第一存储器件。 第三组信号线耦合到第一存储器件和集成电路缓冲器件。 第三多个信号线将第一控制信息从集成电路缓冲器装置传送到第一存储器件。 第一信号线耦合到第一存储器件和集成电路缓冲器件。 第一信号线将来自集成电路缓冲器件的第一信号传送到第一存储器件。 第一信号使来自集成电路缓冲器的第一控制信息与第一存储器件的通信同步。
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公开(公告)号：US07200710B2
公开(公告)日：2007-04-03
申请号：US11130734
申请日：2005-05-17
IPC分类号： G06F12/00
CPC分类号： G11C29/028 , G06F13/1673 , G06F13/1684 , G11C5/04 , G11C7/10 , G11C29/02 , G11C29/50012
摘要： An integrated circuit buffer device comprising a receiver circuit to receive control information and address information. A first interface portion provides at least a first control signal that specifies a write operation to a first memory device. The first control signal corresponds to the control information. A second interface portion provides a first address to the first memory device. The first address corresponds to the address information. The first address specifies a memory location for the write operation to the first memory device. A third interface portion provides a first signal to the first memory device. The first signal synchronizes communication of the first control signal from the integrated circuit buffer device to the first memory device. A fourth interface portion provides at least a second control signal that specifies a write operation to a second memory device. The second control signal corresponds to the control information. A fifth interface portion provides a second address to the second memory device. The second address corresponds to the address information. The second address specifies a memory location for the write operation to the second memory device. A sixth interface portion provides a second signal to the second memory device. The second signal synchronizes communication of the second control signal from the integrated circuit buffer device to the second memory device.
摘要翻译： 一种集成电路缓冲器件，包括用于接收控制信息和地址信息的接收器电路。 第一接口部分至少提供指定对第一存储器件的写入操作的第一控制信号。 第一控制信号对应于控制信息。 第二接口部分向第一存储器件提供第一地址。 第一个地址对应于地址信息。 第一个地址指定用于对第一个存储设备的写入操作的存储器位置。 第三接口部分向第一存储器件提供第一信号。 第一信号使来自集成电路缓冲器的第一控制信号与第一存储器件的通信同步。 第四接口部分至少提供指定对第二存储器件的写入操作的第二控制信号。 第二控制信号对应于控制信息。 第五接口部分向第二存储器件提供第二地址。 第二个地址对应于地址信息。 第二地址指定用于对第二存储设备的写操作的存储器位置。 第六接口部分向第二存储器件提供第二信号。 第二信号使来自集成电路缓冲器的第二控制信号与第二存储器件的通信同步。
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公开(公告)号：US07206897B2
公开(公告)日：2007-04-17
申请号：US11128904
申请日：2005-05-13
IPC分类号： G06F12/00
CPC分类号： G11C29/028 , G06F13/1673 , G06F13/1684 , G11C5/04 , G11C7/10 , G11C29/02 , G11C29/50012
摘要： A memory module includes an integrated circuit buffer device that receives control information via a connector interface. A first plurality of signal lines carries a first address from the integrated circuit buffer device to a first memory device. A second plurality of signal lines carries a first control signal from the integrated circuit buffer device to the first memory device. The first control signal specifies a read operation by the first memory device such that the first memory device provides first data, accessed from a memory location in the first memory device based on the first address, to the integrated circuit buffer device. A first signal line carries a first signal from the integrated circuit buffer device to the first memory device. The first signal synchronizes communication of the first control signal from the integrated circuit buffer device to the first memory device. A third plurality of signal lines carries a second address from the integrated circuit device to the second memory device. A fourth plurality of signal lines carries a second control signal from the integrated circuit buffer device to the second memory device. The second control signal specifies a read operation. The second control signal corresponds to the control information. A second signal line carries a second signal from the integrated circuit buffer device to the second memory device. The second signal synchronizes communication of the second control signal from the integrated circuit buffer device to the second memory device. A transmitter circuit is disposed on the integrated circuit buffer device.
摘要翻译： 存储器模块包括经由连接器接口接收控制信息的集成电路缓冲器装置。 第一多个信号线将第一地址从集成电路缓冲器装置传送到第一存储器件。 第二多个信号线将集成电路缓冲器件的第一控制信号传送到第一存储器件。 第一控制信号指定第一存储器件的读取操作，使得第一存储器件提供从基于第一地址的第一存储器件中的存储器位置访问的第一数据到集成电路缓冲器件。 第一信号线将来自集成电路缓冲器件的第一信号传送到第一存储器件。 第一信号使来自集成电路缓冲器的第一控制信号与第一存储器件的通信同步。 第三组信号线将第二地址从集成电路装置传送到第二存储装置。 第四多个信号线将集成电路缓冲器装置的第二控制信号传送到第二存储装置。 第二控制信号指定读操作。 第二控制信号对应于控制信息。 第二信号线将来自集成电路缓冲器装置的第二信号传送到第二存储装置。 第二信号使来自集成电路缓冲器的第二控制信号与第二存储器件的通信同步。 发射机电路设置在集成电路缓冲装置上。
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公开(公告)号：US07062597B2
公开(公告)日：2006-06-13
申请号：US10625276
申请日：2003-07-23
IPC分类号： G06F12/00
CPC分类号： G11C29/028 , G06F13/1673 , G06F13/1684 , G11C5/04 , G11C7/10 , G11C29/02 , G11C29/50012 , Y02D10/14
摘要： A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device coupled to a plurality of memory devices. The memory system may be upgraded through dedicated point-to-point links and corresponding memory subsystems. The master communicates to the plurality of memory devices in each memory subsystem through the respective buffer device via each point-to-point link.
摘要翻译： 存储器系统架构/互连拓扑，其包括主机和至少一个存储器子系统之间的至少一个点对点链路。 存储器子系统包括耦合到多个存储器件的缓冲器件。 可以通过专用点对点链路和对应的存储器子系统升级存储器系统。 主设备经由每个点到点链路通过相应的缓冲设备与每个存储器子系统中的多个存储器件进行通信。
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5.发明授权System featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices 失效具有控制器装置和存储模块的系统包括集成电路缓冲装置和多个集成电路存储装置公开(公告)号：US07010642B2
公开(公告)日：2006-03-07
申请号：US10952667
申请日：2004-09-28
IPC分类号： G06F12/00
CPC分类号： G11C29/028 , G06F13/1673 , G06F13/1684 , G11C5/04 , G11C7/10 , G11C29/02 , G11C29/50012
摘要： A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device coupled to a plurality of memory devices. The memory system may be upgraded through dedicated point-to-point links and corresponding memory subsystems. The master communicates to the plurality of memory devices in each memory subsystem through the respective buffer device via each point-to-point link
摘要翻译： 存储器系统架构/互连拓扑，其包括主机和至少一个存储器子系统之间的至少一个点对点链路。 存储器子系统包括耦合到多个存储器件的缓冲器件。 可以通过专用点对点链路和对应的存储器子系统升级存储器系统。 主设备经由每个点到点链路通过相应的缓冲设备与每个存储器子系统中的多个存储器件进行通信
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6.发明授权System having a controller device, a buffer device and a plurality of memory devices 失效具有控制器装置，缓冲装置和多个存储装置的系统公开(公告)号：US07523248B2
公开(公告)日：2009-04-21
申请号：US12013160
申请日：2008-01-11
IPC分类号： G06F12/00
CPC分类号： G11C29/028 , G06F13/1673 , G06F13/1684 , G11C5/04 , G11C7/10 , G11C29/02 , G11C29/50012
摘要： A system comprises a controller device, an integrated circuit buffer device and a first and second memory device. A first plurality of signal lines is coupled to the controller device. A second plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The second plurality of signal lines carries first address information from the integrated circuit buffer device to the first memory device. A third plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The third plurality of signal lines carries first control information from the integrated circuit buffer device to the first memory device. A first signal line is coupled to the first memory device and the integrated circuit buffer device. The first signal line carries a first signal from the integrated circuit buffer device to the first memory device. The first signal synchronizes communication of the first control information from the integrated circuit buffer device to the first memory device.
摘要翻译： 一种系统包括控制器装置，集成电路缓冲装置以及第一和第二存储装置。 第一多个信号线耦合到控制器设备。 第二多个信号线耦合到第一存储器件和集成电路缓冲器件。 第二多个信号线将第一地址信息从集成电路缓冲器装置传送到第一存储器件。 第三组信号线耦合到第一存储器件和集成电路缓冲器件。 第三多个信号线将第一控制信息从集成电路缓冲器装置传送到第一存储器件。 第一信号线耦合到第一存储器件和集成电路缓冲器件。 第一信号线将来自集成电路缓冲器件的第一信号传送到第一存储器件。 第一信号使来自集成电路缓冲器的第一控制信息与第一存储器件的通信同步。
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7.发明授权System and method featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices 失效具有控制器装置和存储模块的系统和方法包括集成电路缓冲装置和多个集成电路存储装置公开(公告)号：US07000062B2
公开(公告)日：2006-02-14
申请号：US11054797
申请日：2005-02-10
IPC分类号： G06F12/00
CPC分类号： G11C29/028 , G06F13/1673 , G06F13/1684 , G11C5/04 , G11C7/10 , G11C29/02 , G11C29/50012
摘要： A system comprises a master device and a first integrated circuit buffer device. A first plurality of integrated circuit memory devices are coupled to the first integrated circuit buffer device. A first plurality of signal lines are coupled to the first integrated circuit buffer device and the master device, wherein the first plurality of signal lines communicate control information, address information and data from the master device to the first integrated circuit buffer device. A second plurality of signal lines are coupled to the first integrated circuit buffer device. A second integrated circuit buffer device is coupled to the second plurality of signal lines, the second integrated circuit buffer device receives the control information, the address information and the data from the first integrated circuit buffer device over the second plurality of signal lines. A second plurality of integrated circuit memory devices are coupled to the second integrated circuit buffer device. A third plurality of signal lines are coupled to the first integrated circuit buffer device, the second integrated circuit buffer device and the master device. The third plurality of signal lines communicate information from the master device that initialize the first integrated circuit buffer device and the second integrated circuit buffer device.
摘要翻译： 系统包括主设备和第一集成电路缓冲设备。 第一组多个集成电路存储器件耦合到第一集成电路缓冲器件。 第一多个信号线耦合到第一集成电路缓冲器装置和主装置，其中第一多个信号线将控制信息，地址信息和数据从主装置传送到第一集成电路缓冲装置。 第二组多个信号线耦合到第一集成电路缓冲器件。 第二集成电路缓冲器件耦合到第二多个信号线，第二集成电路缓冲器件通过第二多个信号线从第一集成电路缓冲器件接收控制信息，地址信息和数据。 第二组多个集成电路存储器件耦合到第二集成电路缓冲器件。 第三组信号线耦合到第一集成电路缓冲器件，第二集成电路缓冲器件和主器件。 第三多个信号线传送来自初始化第一集成电路缓冲装置和第二集成电路缓冲装置的主装置的信息。
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公开(公告)号：US06832284B1
公开(公告)日：2004-12-14
申请号：US10625276
申请日：2003-07-23
IPC分类号： G06F1200
摘要： A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device coupled to a plurality of memory devices. The memory system may be upgraded through dedicated point-to-point links and corresponding memory subsystems. The master communicates to the plurality of memory devices in each memory subsystem through the respective buffer device via each point-to-point link.
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公开(公告)号：US06502161B1
公开(公告)日：2002-12-31
申请号：US09479375
申请日：2000-01-05
IPC分类号： G06F1200
CPC分类号： G11C29/028 , G06F13/1673 , G06F13/1684 , G11C5/04 , G11C7/10 , G11C29/02 , G11C29/50012 , Y02D10/14
摘要： A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device coupled to a plurality of memory devices. The memory system may be upgraded through dedicated point-to-point links and corresponding memory subsystems. The master communicates to the plurality of memory devices in each memory subsystem through the respective buffer device via each point-to-point link.
摘要翻译： 存储器系统架构/互连拓扑，其包括主机和至少一个存储器子系统之间的至少一个点对点链路。 存储器子系统包括耦合到多个存储器件的缓冲器件。 可以通过专用点对点链路和对应的存储器子系统升级存储器系统。 主设备经由每个点到点链路通过相应的缓冲设备与每个存储器子系统中的多个存储器件进行通信。
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10.发明申请System Having A Controller Device, A Buffer Device And A Plurality Of Memory Devices 审中-公开具有控制器装置，缓冲器装置和多种存储器件的系统公开(公告)号：US20090319719A1
公开(公告)日：2009-12-24
申请号：US12411003
申请日：2009-03-25
IPC分类号： G06F12/06
CPC分类号： G11C29/028 , G06F13/1673 , G06F13/1684 , G11C5/04 , G11C7/10 , G11C29/02 , G11C29/50012
摘要： A system comprises a controller device, an integrated circuit buffer device and a first and second memory device. A first plurality of signal lines is coupled to the controller device. A second plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The second plurality of signal lines carries first address information from the integrated circuit buffer device to the first memory device. A third plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The third plurality of signal lines carries first control information from the integrated circuit buffer device to the first memory device. A first signal line is coupled to the first memory device and the integrated circuit buffer device. The first signal line carries a first signal from the integrated circuit buffer device to the first memory device. The first signal synchronizes communication of the first control information from the integrated circuit buffer device to the first memory device.
摘要翻译： 一种系统包括控制器装置，集成电路缓冲装置以及第一和第二存储装置。 第一多个信号线耦合到控制器设备。 第二多个信号线耦合到第一存储器件和集成电路缓冲器件。 第二多个信号线将第一地址信息从集成电路缓冲器装置传送到第一存储器件。 第三组信号线耦合到第一存储器件和集成电路缓冲器件。 第三多个信号线将第一控制信息从集成电路缓冲器装置传送到第一存储器件。 第一信号线耦合到第一存储器件和集成电路缓冲器件。 第一信号线将来自集成电路缓冲器件的第一信号传送到第一存储器件。 第一信号使来自集成电路缓冲器的第一控制信息与第一存储器件的通信同步。
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