-
1.发明授权Method and apparatus for tracing unpredictable execution flows in a trace buffer of a high-speed computer system 失效用于在高速计算机系统的跟踪缓冲器中跟踪不可预测的执行流的方法和装置
公开(公告)号：US5802272A
公开(公告)日：1998-09-01
申请号：US359252
申请日：1994-12-19
CPC分类号： G06F11/3636 , G06F11/3466 , G06F2201/865
摘要： An operation of a processor is traced while fetching instructions from a memory to operate the processor. The tracing involves detecting an unpredictable fetching of instructions on the assumption that a predictable fetching can be reconstructed without any further input. The unpredictable fetching is identified as being due to either computable, conditional, or unanticipated events. Upon detecting the events, process control information, such as the next instruction to be fetched is recorded in a queue, and from the queue the information can be stored in a trace buffer. During reconstruction of the operation, the trace buffer, and the image including the instructions can be examined to analyze the real-time operation of the processor.
摘要翻译： 在从存储器取指令以操作处理器的同时追踪处理器的操作。 跟踪涉及检测指令的不可预测的取指，假设可以重建无法进一步输入的可预测提取。 不可预测的提取被识别为由于可计算的，有条件的或意外的事件。 在检测到事件时，诸如要获取的下一个指令的处理控制信息被记录在队列中，并且从队列中可以将信息存储在跟踪缓冲器中。 在重建操作期间，可以检查跟踪缓冲区和包括指令的图像，以分析处理器的实时操作。
-
2.发明授权
公开(公告)号：US5764885A
公开(公告)日：1998-06-09
申请号：US359216
申请日：1994-12-19
CPC分类号： G06F11/3636
摘要： A data flow of a processor is traced while accessing data stored in a memory and in a plurality of registers during operation of the processor. The tracing involves detecting an unpredictable accessing of data on the assumption that a predictable accessing can be reconstructed without any further input. The unpredictable accessing is identified by setting and clearing a trace bit associated with each of the registers according to identifying the accessing as direct memory-to-register, register-to-register, constant-to-register, and indirect memory. If a trace bit is set on a register storing data being used as a base address during the indirect memory acceding, data flow control information, such as the base address stored in the register being used during the indirect acceding is recorded in a queue, and from the queue the information can be stored in a trace buffer. During reconstruction of the operation, the trace buffer, and a copy of the data having an initial state can be examined to analyze the data flows during the real-time operation of the processor.
摘要翻译： 在处理器的操作期间，访问处理器的数据流，同时访问存储在存储器中以及多个寄存器中的数据。 跟踪涉及检测数据的不可预知的访问，假设可以重建可预测的访问而无需任何进一步的输入。 通过根据将访问识别为直接存储器到寄存器，寄存器到寄存器，恒定寄存器和间接存储器来设置和清除与每个寄存器相关联的跟踪位来识别不可预测的访问。 如果在间接存储器加入期间在存储用作基地址的数据的寄存器上设置跟踪位，则将间接加入期间使用的存储在寄存器中的基地址的数据流控制信息记录在队列中， 从队列中可以将信息存储在跟踪缓冲区中。 在重构操作期间，可以检查跟踪缓冲器和具有初始状态的数据的副本，以在处理器的实时操作期间分析数据流。
-
搜索结果
2 条记录 (耗时 0.02 秒)
