公开(公告)号：US12160151B2

公开(公告)日：2024-12-03

申请号：US17512896

申请日：2021-10-28

Applicant: Richtek Technology Corporation

Inventor： Tsung-Han Yang ,  Yen-Chih Wang ,  Ming-Jun Hsiao ,  Tsung-Nan Wu

IPC: H02P25/034 ,  H02K33/04 ,  H02P6/00 ,  H02P25/06

Abstract: An electronic device for controlling an LRA (Linear Resonant Actuator) includes a signal generator, a driver, a delay unit, a sensor, and a DSP (Digital Signal Processor). The signal generator generates a digital signal. The driver drives the LRA according to the digital signal. The delay unit delays the digital signal for a predetermined time, so as to generate an estimated voltage signal. The sensor detects the current flowing through the LRA, so as to generate a sensing current signal. The DSP controls the resonant frequency or the gain value of the signal generator according to the estimated voltage signal and the sensing current signal.

公开(公告)号：US11323299B2

公开(公告)日：2022-05-03

申请号：US17337351

申请日：2021-06-02

Applicant: Richtek Technology Corporation

Inventor： Hung-Chi Huang ,  Fu-Chi Lin ,  Tsung-Nan Wu ,  Mei-Shu Wang

IPC: H04L27/06 ,  H04L27/156 ,  H04L1/00

Abstract: A communication signal demodulation apparatus demodulates a communication signal to generate an output signal. The communication signal demodulation apparatus includes: plural sensor circuits which sense different electrical characteristics of one same communication signal and generate corresponding sensing modulation signals respectively; plural processing filters which filter the corresponding sensing modulation signals respectively and generate corresponding filtered modulation signals respectively; plural demodulators which demodulate the plural filtered modulation signals and generate corresponding demodulation signals respectively, wherein each of the filtered modulation signals corresponds to at least one of the demodulators; and a determination circuit which receive the plural demodulation signals, determine whether each unit signal of each of the demodulation signals is correct or not according to a determination mechanism, and combine one or more correct unit signals to generate the output signal.

公开(公告)号：US09124971B2

公开(公告)日：2015-09-01

申请号：US13965518

申请日：2013-08-13

Applicant: Richtek Technology Corporation

Inventor： Tsung-Nan Wu

IPC: H04R5/00 ,  H04R5/04 ,  G10L19/00 ,  H03F3/217

CPC classification number: H04R5/04 ,  G10L19/00 ,  H03F3/217

Abstract: An audio signal processing circuit includes an encoding circuit, a first audio conversion circuit, and a second audio conversion circuit. The encoding circuit receives pulse coded modulation signals and generates a first audio signal and a second audio signal accordingly. The first audio conversion circuit generates a first pulse width modulation (PWM) signal according to consecutive values of the first audio signal for configuring a first power stage circuit. The second audio conversion circuit generates a second PWM signal according to consecutive values of the second audio signal for configuring a second power stage circuit. The pulse width of the first PWM signal is configured to be substantially equal to the pulse width of the second PWM signal, and the pulse edges of the first PWM signal and the second PWM signal are configured to be separated by a predetermined time interval to mute the audio signal processing circuit.

Abstract translation: 音频信号处理电路包括编码电路，第一音频转换电路和第二音频转换电路。 编码电路接收脉冲编码的调制信号，并相应地产生第一音频信号和第二音频信号。 第一音频转换电路根据用于配置第一功率级电路的第一音频信号的连续值产生第一脉冲宽度调制（PWM）信号。 第二音频转换电路根据用于配置第二功率级电路的第二音频信号的连续值产生第二PWM信号。 第一PWM信号的脉冲宽度被配置为基本上等于第二PWM信号的脉冲宽度，并且第一PWM信号和第二PWM信号的脉冲边缘被配置为以预定的时间间隔隔开以静音 音频信号处理电路。