公开(公告)号：US20250167740A1

公开(公告)日：2025-05-22

申请号：US18644121

申请日：2024-04-24

Applicant: Richtek Technology Corporation

Inventor： Wen-Hsuan Chang ,  Yi-Kuang Chen

IPC: H03F3/217

Abstract: A class-D amplifier for generating an output signal having PWM according to an input signal based on a DC voltage during a normal mode (NM) includes: a first integrator for generating a first integrated signal by integrating the difference of the input signal and a feedback signal during the NM; a final-stage integrator for generating a final-stage integrated signal by integrating the first integrated signal during the NM; a superposition circuit for generating a loop filter signal by buffering the final-stage integrated signal during the NM; and a modulation and driving circuit for generating the output signal by comparing the loop filter signal and a triangle wave. During a clipping mode, the first integrator enters a reset or a hold state, and the final-stage integrator enters the hold state, and the superposition circuit is configured to superimposes the final-stage integrated signal and a feedforward signal to generate the loop filter signal.