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1.发明授权Stacked via Kelvin resistance test structure for measuring contact anomalies in multi-level metal integrated circuit technologies 有权通过开尔文电阻测试结构堆叠，用于测量多级金属集成电路技术中的接触异常公开(公告)号：US06362638B1
公开(公告)日：2002-03-26
申请号：US09388203
申请日：1999-09-01
IPC分类号： G01R3126
CPC分类号： G01R31/04
摘要： A method and apparatus for measuring Kelvin contact resistance within an integrated circuit interconnect is provided, having upper and lower Kelvin contact resistance contacts covering a via and interconnect being measured, along with a third conductor placed substantially between the upper and lower Kelvin contacts, and in contact with the via.
摘要翻译： 提供了一种用于测量集成电路互连中的开尔文接触电阻的方法和装置，具有覆盖通过测量的通孔和互连的上开和下开口接触电阻触点，以及基本上位于上开和下开口触点之间的第三导体，以及 与通道接触。
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2.发明授权公开(公告)号：US06329281B1
公开(公告)日：2001-12-11
申请号：US09454909
申请日：1999-12-03
IPC分类号： H01L214763
CPC分类号： H01L21/76807 , H01L21/76813
摘要： The present invention utilizes a selective overlayer to provide more efficient fabrication of a dual damascene multilevel interconnect structure. The selective overlayer serves as a protective mask which prevents the upper layer of the composite layer from being eroded during the formation of the multi-level interconnects. The present invention also solves some of the problems associated with the full-via first and partial-via first fabrication methods because the selective overlayer enables an efficient, deep partial via to be formed while preventing the deposit of undeveloped photoresist in subsequent fabrication steps. The present invention also provides advantages during the planarization and polishing of the dual damascene structure after the deposition of the conductive layer because the selective overlayer allows for efficient planarization without loss of trench depth control.
摘要翻译： 本发明利用选择性覆盖层来提供更有效地制造双镶嵌多层互连结构。 选择性覆盖层用作保护掩模，其防止复合层的上层在形成多层互连期间被侵蚀。 本发明还解决了与全通孔第一和部分通孔第一制造方法相关的一些问题，因为选择性覆盖层能够形成有效的深部分通孔，同时防止在随后的制造步骤中沉积未显影的光致抗蚀剂。 本发明还在沉积导电层之后在双镶嵌结构的平面化和抛光期间提供了优点，因为选择性覆盖层允许有效的平面化而不损失沟槽深度控制。
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