公开(公告)号：US4383295A

公开(公告)日：1983-05-10

申请号：US11001

申请日：1979-02-09

申请人： Robert C. Miller ,  John J. Bradley ,  Boyd E. Darden ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

发明人： Robert C. Miller ,  John J. Bradley ,  Boyd E. Darden ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

IPC分类号： G06F3/02 ,  G06F9/06

CPC分类号： G06F3/0227

摘要： In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processor unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and later provides the CPU with a channel number assigned to the requesting IOC. In order to allow a data entry operator inputting data via a peripheral device connected to an IOC the ability to correct errors, a backspace character is provided so that the operator can enter it to indicate to the system to ignore the preceding character. Logic is provided within the system to allow a DMC IOC to detect the output of a backspace character from the peripheral device connected to the IOC and to inform the CPU of the entry of the backspace character by a special (backspace) input/output interrupt. Further logic is provided within the CPU to adjust pointers to the main memory input buffer to effectively ignore the byte of data corresponding to the character preceding the backspace character. Still further logic is provided within the DMC IOC to prohibit the sending of special (backspace) input/output interrupts to the CPU if there are no bytes of data remaining in the input buffer.

摘要翻译： 在包括一个或多个公共总线的数据处理系统中，多个输入/输出控制器连接到该公共总线用于传送数据，数据块可以在主存储器和与操作同步的输入/输出控制器（IOC）之间传送 的中央处理器单元（CPU）。 提供逻辑用于在数据复用控制（DMC）数据传输操作期间传输一个数据单元，其中请求的IOC请求CPU的DMC数据传输，并且稍后向CPU提供分配给请求的IOC的通道号 。 为了允许数据输入操作者通过连接到IOC的外围设备输入数据以校正错误的能力，提供退格字符，以便操作者可以进入它以指示系统忽略前一个字符。 在系统中提供逻辑，以允许DMC IOC从连接到IOC的外围设备检测退格字符的输出，并通过特殊（退格）输入/输出中断向CPU通知退格字符的输入。 在CPU内提供进一步的逻辑来调整指向主存储器输入缓冲器的指针，以有效地忽略与退格字符之前的字符相对应的数据字节。 在DMC IOC中还提供了一些逻辑，以禁止在CPU中输入/输出特殊的（空格）输入/输出中断，如果输入缓冲区中没有字节数据。

公开(公告)号：US4295194A

公开(公告)日：1981-10-13

申请号：US73056

申请日：1979-09-06

申请人： Boyd E. Darden ,  Henry F. Hartley

发明人： Boyd E. Darden ,  Henry F. Hartley

IPC分类号： G06F9/48 ,  G06F9/46

CPC分类号： G06F9/4825

摘要： A data processing system includes a central processing unit, a main store and device controllers which couple to a bus system. Each controller has a number of device adapter units. One controller includes a real time adapter unit which instead of being connected to control a peripheral device is connected to provide a timer facility for use by the central processing unit (CPU) in executing tasks. The real time adapter unit includes a microprocessing section, a timer section, and a module time of day section. The time of day includes circuits which are connected to provide accurate and reliable time of day values. The timer module section includes circuits which are connected to provide variable time intervals. The circuits of both sections are connected to the circuits of the microprocessing section. In response to a number of different commands received from the central processing unit, the microprocessing unit (MPU) of the microprocessing section loads the various registers included within the timer module section to establish a desired interval at which it is to monitor the time of day operation of the time of day section. When the microprocessing unit establishes that the particular time of day operation specified by the central processing unit has been completed, it generates signals for notifying the central processing unit.

摘要翻译： 数据处理系统包括中央处理单元，主存储器和耦合到总线系统的设备控制器。 每个控制器都有多个设备适配器单元。 一个控制器包括实时适配器单元，而不是连接到控制外围设备的连接器，以提供定时器设施供中央处理单元（CPU）执行任务使用。 实时适配器单元包括微处理部分，定时器部分和模块时间段。 一天中的时间包括连接到提供准确和可靠的时间值的电路。 定时器模块部分包括连接以提供可变时间间隔的电路。 两部分的电路连接到微处理部分的电路。 响应于从中央处理单元接收到的多个不同的命令，微处理部分的微处理单元（MPU）加载包括在定时器模块部分内的各种寄存器，以建立期望监视时间的间隔 时间段操作。 当微处理单元确定由中央处理单元指定的特定时间操作已经完成时，它产生用于通知中央处理单元的信号。

公开(公告)号：US4287562A

公开(公告)日：1981-09-01

申请号：US73058

申请日：1979-09-06

申请人： Boyd E. Darden ,  Henry F. Hartley

发明人： Boyd E. Darden ,  Henry F. Hartley

IPC分类号： G06F9/48 ,  G06F13/12 ,  G06F3/00

CPC分类号： G06F9/4825 ,  G06F13/12

摘要： A data processing system includes a central processing unit, a main store and device controllers which couple to a bus system. Each controller has a number of device adapter units. One controller includes a real time adapter unit which instead of being connected to control a peripheral device is connected to provide a timer facility for use by the central processing unit in executing tasks. The real time adapter unit includes microprocessing circuits and clock circuits. These circuits are connected to provide accurate and reliable time of day values in response to commands from the central processing unit.

摘要翻译： 数据处理系统包括中央处理单元，主存储器和耦合到总线系统的设备控制器。 每个控制器都有多个设备适配器单元。 一个控制器包括实时适配器单元，而不是连接到控制外围设备的连接器，以提供中央处理单元在执行任务中使用的定时器设备。 实时适配器单元包括微处理电路和时钟电路。 这些电路被连接以响应于来自中央处理单元的命令提供准确和可靠的时间值。