公开(公告)号：US06574779B2

公开(公告)日：2003-06-03

申请号：US09833479

申请日：2001-04-12

申请人： Robert J. Allen ,  John M. Cohn ,  Steve G. Lovejoy

发明人： Robert J. Allen ,  John M. Cohn ,  Steve G. Lovejoy

IPC分类号： G06F1750

CPC分类号： G06F17/5068

摘要： A method for hierarchical layout of an electronic design using an electronic computer aided design system, wherein the method includes generating a parameterized pattern library and using an existing netlist and analyze in a pattern recognizer, from which a list of associations between the pattern library and the netlist is created. Renesting then occurs wherein the netlist using the list of associations is used for generating a hierarchical layout of the electronic components in the design.