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公开(公告)号：US20060262590A1
公开(公告)日：2006-11-23
申请号：US11115538
申请日：2005-04-27
IPC分类号： G11C17/00
CPC分类号： G11C17/16
摘要： A one-time programmable circuit uses forced BJT hFE degradation to permanently store digital information as a logic zero or logic one state. The forced degradation is accomplished by applying a voltage or current to the BJT for a specific time to the reversed biased base-emitter junction, allowing a significant degradation of the junction without destroying it.
摘要翻译： 一次性可编程电路使用强制BJT低电平劣化将数字信息永久存储为逻辑0或逻辑1状态。 强制退化是通过向BJT施加一个特定时间的电压或电流到反向偏置的基极 - 发射极接点来实现的，从而允许接合处的显着劣化而不破坏它。
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公开(公告)号：US07292066B2
公开(公告)日：2007-11-06
申请号：US11115538
申请日：2005-04-27
IPC分类号： H03K19/082
CPC分类号： G11C17/16
摘要： A one-time programmable circuit uses forced BJT hFE degradation to permanently store digital information as a logic zero or logic one state. The forced degradation is accomplished by applying a voltage or current to the BJT for a specific time to the reversed biased base-emitter junction, allowing a significant degradation of the junction without destroying it.
摘要翻译： 一次性可编程电路使用强制BJT低电平劣化将数字信息永久存储为逻辑0或逻辑1状态。 强制退化是通过向BJT施加一个特定时间的电压或电流到反向偏置的基极 - 发射极接点来实现的，从而允许接合处的显着劣化而不破坏它。
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公开(公告)号：US06365946B1
公开(公告)日：2002-04-02
申请号：US09311339
申请日：1999-05-13
IPC分类号： H01L2976
CPC分类号： H01L21/76224
摘要： An IC isolation structure includes a recess disposed in a conductive layer having a surface portion. The recess has a side wall adjacent to the surface portion, and the isolation structure also includes an insulator disposed in the recess and overlapping the surface portion. Thus, if a transistor is disposed in the conductive layer adjacent to the recess side wall, the overlapping portion of the insulator increases the distance between the upper recess corner and the gate electrode. This increased distance reduces hump effects to tolerable levels.
摘要翻译： IC隔离结构包括设置在具有表面部分的导电层中的凹部。 凹部具有与表面部分相邻的侧壁，并且隔离结构还包括设置在凹部中并与表面部分重叠的绝缘体。 因此，如果在与凹槽侧壁相邻的导电层中设置晶体管，则绝缘体的重叠部分增加了上凹部角部和栅电极之间的距离。 这种增加的距离将驼峰效应降低到可承受的水平。
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