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公开(公告)号：US20100017547A1
公开(公告)日：2010-01-21
申请号：US12177000
申请日：2008-07-21
IPC分类号： G06F13/40
CPC分类号： G06F13/4045
摘要： Various apparatuses, methods and systems for specifying memory transaction sizes on a PCI bus are disclosed herein. For example, some embodiments of the present invention provide apparatuses for transferring data including a PCI bus, a memory map for memory transactions performed on the PCI bus, and at least one set of control registers adapted to establish at least one window within the memory map. The set of control registers contains an address range for the at least one window within the memory map and a burst transfer size for memory transactions taking place on the PCI bus that are addressed within the address range.
摘要翻译： 本文公开了用于指定PCI总线上的存储器事务大小的各种装置，方法和系统。 例如，本发明的一些实施例提供用于传送包括PCI总线，用于在PCI总线上执行的存储器事务的存储器映射的数据的数据的装置，以及适于在存储器映射中建立至少一个窗口的至少一组控制寄存器 。 该组控制寄存器包含存储器映射内的至少一个窗口的地址范围，以及在地址范围内寻址的PCI总线上发生的存储器事务的突发传送大小。
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公开(公告)号：US20080162836A1
公开(公告)日：2008-07-03
申请号：US11648701
申请日：2006-12-29
申请人： Roy D. Wojciechowski , Asad Khan
发明人： Roy D. Wojciechowski , Asad Khan
IPC分类号： G06F13/00
CPC分类号： G06F13/4234
摘要： Methods and systems are provided for receiving and assembling serial data into parallel arrangements referred to as data slices. A plurality of data slices define a data line. Data slices common to a data line are written across like addresses of memory logically partitioned as memory slots. Respective memory slots are selected for data write operations in a successively advancing manner. As a result, a just-written data slice is immediately available for reading on the next clock cycle. Also, respective data slices can be simultaneously written to and read from the same or different memory slots on a particular clock cycle. Fast serial data communication between peripheral devices and other computer-related entities is performed accordingly.
摘要翻译： 方法和系统被提供用于将串行数据接收和组装成被称为数据切片的并行布置。 多个数据片段定义数据线。 将与数据线相同的数据切片写入逻辑划分为存储器槽的存储器的相同地址。 以连续前进的方式选择相应的存储器插槽用于数据写入操作。 因此，在下一个时钟周期内，立即可以读取刚刚写入的数据片。 此外，各个数据片可以在特定时钟周期上同时写入和读取相同或不同的存储器时隙。 相应地执行外围设备与其他计算机相关实体之间的快速串行数据通信。
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公开(公告)号：US07877536B2
公开(公告)日：2011-01-25
申请号：US11964609
申请日：2007-12-26
CPC分类号： G06F13/4221
摘要： A Peripheral Component Interconnect (PCI) Express switch is provided. The PCI Express switch includes a first routing information bus connected to the first port; a second routing information bus connected to the second port; a third routing information bus connected to the third port; two routing slaves in the first port, each dedicated to listening to one of the second and the third routing information buses; two routing slaves in the second port, each dedicated to listening to one of the first and the third routing information buses; and two routing slaves in the third port, each dedicated to listening to one of the first and the second routing information buses.
摘要翻译： 提供外设部件互连（PCI）Express交换机。 PCI Express交换机包括连接到第一端口的第一路由信息总线; 连接到第二端口的第二路由信息总线; 连接到第三端口的第三路由信息总线; 第一端口中的两个路由从站，每个专用于监听第二和第三路由信息总线中的一个; 第二端口中的两个路由从站，每个专用于监听第一和第三路由信息总线之一; 以及第三端口中的两个路由从站，每个专用于监听第一和第二路由信息总线之一。
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公开(公告)号：US20090172237A1
公开(公告)日：2009-07-02
申请号：US11964609
申请日：2007-12-26
IPC分类号： G06F13/14
CPC分类号： G06F13/4221
摘要： A Peripheral Component Interconnect (PCI) Express switch is provided. The PCI Express switch includes a first routing information bus connected to the first port; a second routing information bus connected to the second port; a third routing information bus connected to the third port; two routing slaves in the first port, each dedicated to listening to one of the second and the third routing information buses; two routing slaves in the second port, each dedicated to listening to one of the first and the third routing information buses; and two routing slaves in the third port, each dedicated to listening to one of the first and the second routing information buses.
摘要翻译： 提供外设组件互连（PCI）Express交换机。 PCI Express交换机包括连接到第一端口的第一路由信息总线; 连接到第二端口的第二路由信息总线; 连接到第三端口的第三路由信息总线; 第一端口中的两个路由从站，每个专用于监听第二和第三路由信息总线中的一个; 第二端口中的两个路由从站，每个专用于监听第一和第三路由信息总线之一; 以及第三端口中的两个路由从站，每个专用于监听第一和第二路由信息总线之一。
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公开(公告)号：US20080162769A1
公开(公告)日：2008-07-03
申请号：US11967086
申请日：2007-12-29
申请人： Roy D. Wojciechowski
发明人： Roy D. Wojciechowski
IPC分类号： G06F13/28
CPC分类号： G06F13/4059
摘要： Systems and methods are disclosed for detecting a first device on a first bus issuing a read request for an amount of data to a second device on a second bus. The systems and methods further include detecting a bridge requesting a first portion of the data from the second device on behalf of the first device in response to the bridge receiving the read request, where the bridge couples the first bus to the second bus. In addition, the systems and methods include triggering the bridge to request an additional portion of the data on behalf of the first device.
摘要翻译： 公开了用于检测在第二总线上向第二设备发出数据量的读请求的第一总线上的第一设备的系统和方法。 所述系统和方法还包括响应于所述桥接器接收所述读请求，检测代表所述第一设备从所述第二设备请求所述数据的第一部分的桥，其中所述桥将所述第一总线耦合到所述第二总线。 此外，系统和方法包括触发桥接器代表第一设备请求附加的数据部分。
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公开(公告)号：US07814258B2
公开(公告)日：2010-10-12
申请号：US12177000
申请日：2008-07-21
CPC分类号： G06F13/4045
摘要： Various apparatuses, methods and systems for specifying memory transaction sizes on a PCI bus are disclosed herein. For example, some embodiments of the present invention provide apparatuses for transferring data including a PCI bus, a memory map for memory transactions performed on the PCI bus, and at least one set of control registers adapted to establish at least one window within the memory map. The set of control registers contains an address range for the at least one window within the memory map and a burst transfer size for memory transactions taking place on the PCI bus that are addressed within the address range.
摘要翻译： 本文公开了用于指定PCI总线上的存储器事务大小的各种装置，方法和系统。 例如，本发明的一些实施例提供用于传送包括PCI总线，用于在PCI总线上执行的存储器事务的存储器映射的数据的数据的装置，以及适于在存储器映射中建立至少一个窗口的至少一组控制寄存器 。 该组控制寄存器包含存储器映射内的至少一个窗口的地址范围，以及在地址范围内寻址的PCI总线上发生的存储器事务的突发传送大小。
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7.发明授权公开(公告)号：US07730361B2
公开(公告)日：2010-06-01
申请号：US11693781
申请日：2007-03-30
CPC分类号： G06F13/4247 , G06F11/0745 , G06F11/0772 , G06F11/0781
摘要： A method of aggregating events in a PCIe (Peripheral Component Interconnect Express) multifunction device minimizes reported error messages, where several functions share a common PCIe interface logic. A predetermined number of function entities with logical gates, connected in daisy chain configuration, process incoming information, and a decision is made whether each function entity will generate a blocking control or a pass-through control. The error messages are aggregated across the function entities in a single clock cycle with the help of an error controller. The functions can be from IEEE 1394 interface, graphics display controller, sound card, PCIe switch, or PCIe to PCI bridge connection. Each function preferably has a different configuration and security level setting for error reporting and messaging. There may be a plurality of parallel daisy chains, and the PCIe device may include three layers namely, a physical layer, data link layer and transaction protocol layer (for error logging, reporting).
摘要翻译： 在PCIe（外围部件互联互连Express）多功能设备中聚合事件的方法将报告的错误消息最小化，其中多个功能共享公共PCIe接口逻辑。 具有以菊花链配置连接的逻辑门，处理传入信息和决定的预定数量的功能实体是确定每个功能实体是否将生成阻塞控制或直通控制。 在错误控制器的帮助下，错误消息在单个时钟周期内跨功能实体进行聚合。 这些功能可以来自IEEE 1394接口，图形显示控制器，声卡，PCIe交换机或PCIe到PCI桥连接。 每个功能优选地具有用于错误报告和消息传递的不同配置和安全级别设置。 可以存在多个并行菊花链，并且PCIe设备可以包括三层，即物理层，数据链路层和事务协议层（用于错误记录，报告）。
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公开(公告)号：US07711888B2
公开(公告)日：2010-05-04
申请号：US11967086
申请日：2007-12-29
申请人： Roy D. Wojciechowski
发明人： Roy D. Wojciechowski
IPC分类号： G06F13/00
CPC分类号： G06F13/4059
摘要： Systems and methods are disclosed for detecting a first device on a first bus issuing a read request for an amount of data to a second device on a second bus. The systems and methods further include detecting a bridge requesting a first portion of the data from the second device on behalf of the first device in response to the bridge receiving the read request, where the bridge couples the first bus to the second bus. In addition, the systems and methods include triggering the bridge to request an additional portion of the data on behalf of the first device.
摘要翻译： 公开了用于检测在第二总线上向第二设备发出数据量的读请求的第一总线上的第一设备的系统和方法。 所述系统和方法还包括响应于所述桥接器接收所述读请求，检测代表所述第一设备从所述第二设备请求所述数据的第一部分的桥，其中所述桥将所述第一总线耦合到所述第二总线。 此外，系统和方法包括触发桥接器代表第一设备请求附加的数据部分。
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公开(公告)号：US07433984B2
公开(公告)日：2008-10-07
申请号：US10965035
申请日：2004-10-13
申请人： Sumit Das , Kevin Main , Roy D. Wojciechowski
发明人： Sumit Das , Kevin Main , Roy D. Wojciechowski
IPC分类号： G06F13/36
CPC分类号： G06F13/372
摘要： A PCI bus time-based weighted round robin arbiter has a phase table divided into a plurality of phases. Each of the phases is assigned to one of the ports on the PCI bus. An arbiter state machine is coupled to the phase table and looks at the port assignment for the next plurality of phases, for example, 3 phases. If the arbiter determines that the next plurality of phases is assigned to a single port, that port is selected as the next bus master.
摘要翻译： PCI总线基于时间的加权循环仲裁器具有被分成多个阶段的相位表。 每个相位分配给PCI总线上的一个端口。 仲裁器状态机耦合到相位表，并查看下一个多个相位的端口分配，例如3相。 如果仲裁者确定下一个多个阶段被分配给单个端口，则该端口被选择为下一个总线主机。
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