Abstract:
A display device includes: pixels; gate lines for connecting to the pixels; a first gate driving block for connecting to first and second gate lines that are adjacent to each other; and a second gate driving block for connecting to the first gate line and the second gate line, wherein the first gate driving block includes: a first gate signal generating portion; a first transistor connected between a first output terminal of the first gate signal generating portion and the first gate line; and a second transistor connected between the first output terminal and the second gate line, wherein the second gate driving block includes: a second gate signal generating portion; a third transistor connected between a second output terminal of the second gate signal generating portion and the first gate line; and a fourth transistor connected between the second output terminal and the second gate line.
Abstract:
A display device includes: pixels; gate lines for connecting to the pixels; a first gate driving block for connecting to first and second gate lines that are adjacent to each other; and a second gate driving block for connecting to the first gate line and the second gate line, wherein the first gate driving block includes: a first gate signal generating portion; a first transistor connected between a first output terminal of the first gate signal generating portion and the first gate line; and a second transistor connected between the first output terminal and the second gate line, wherein the second gate driving block includes: a second gate signal generating portion; a third transistor connected between a second output terminal of the second gate signal generating portion and the first gate line; and a fourth transistor connected between the second output terminal and the second gate line.
Abstract:
A display device is provided including a timing controller configured to output a test image signal, a data driver configured to output a plurality of data voltages corresponding to the test image signal; and a display panel configured to display a test image corresponding to the data voltages, wherein the timing controller includes a first processor configured to output the test image signal in response to a test signal, and a second processor configured to receive luminance information of the test image, correct a predetermined reference gamma voltage corresponding to the test image with reference to the received luminance information, and output the test signal, which corresponds to the reference gamma voltage, to the first processor.
Abstract:
A method of driving a display panel includes compensating first pixel data corresponding to a first pixel of a plurality of pixels in the display panel based on at least one of a first decision, a second decision, or a third decision and generating a first data voltage corresponding to the compensated first pixel data. The first data voltage is applied to the first pixel through a data line. The first decision includes determining, based on a position of the first pixel, whether compensation for the first pixel data is required. The second decision includes determining, based on previous subpixel data and present subpixel data for the first pixel, whether the compensation for the first pixel data is required. The third decision includes determining whether the first pixel data complies with a compensation avoidance condition.