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公开(公告)号：US20170287432A1
公开(公告)日：2017-10-05
申请号：US15470968
申请日：2017-03-28
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： JIHEE YOON , Kang-woo Kim , Beomjun Kim , Jonghwan Lee , Hong-woo Lee
CPC classification number: G09G3/3696 , G09G3/2074 , G09G3/3614 , G09G3/3659 , G09G3/3677 , G09G3/3688 , G09G2300/0852 , G09G2310/0205
Abstract: A display device includes a display panel having a plurality of pixels respectively connected to a plurality of gate lines and a plurality of data lines, a gate driving circuit that outputs a plurality of gate signals to the plurality of gate lines, and a data driving circuit configured that outputs a plurality of data signals for driving the plurality of data lines. Each of the plurality of pixels includes a first sub-pixel configured to receive a corresponding data signal among the plurality of data signals in response to a first gate signal among the plurality of gate signals, and a second sub-pixel configured to receive a corresponding data signal among the plurality of data signals in response to the first gate signal, and reduce a voltage of the received data signal in response to a second gate signal among the plurality of gate signals. The second gate signal is a signal delayed by a 2×d×H time relative to the first gate signal (where each of d and H is a positive integer, H is a horizontal period, and d×H is a pulse width of first and second gate signals).
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公开(公告)号：US10269321B2
公开(公告)日：2019-04-23
申请号：US15470968
申请日：2017-03-28
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Jihee Yoon , Kang-woo Kim , Beomjun Kim , Jonghwan Lee , Hong-woo Lee
Abstract: A display device includes a display panel having a plurality of pixels respectively connected to a plurality of gate lines and a plurality of data lines, a gate driving circuit that outputs a plurality of gate signals to the plurality of gate lines, and a data driving circuit configured that outputs a plurality of data signals for driving the plurality of data lines. Each of the plurality of pixels includes a first sub-pixel configured to receive a corresponding data signal among the plurality of data signals in response to a first gate signal among the plurality of gate signals, and a second sub-pixel configured to receive a corresponding data signal among the plurality of data signals in response to the first gate signal, and reduce a voltage of the received data signal in response to a second gate signal among the plurality of gate signals. The second gate signal is a signal delayed by a 2×d×H time relative to the first gate signal (where each of d and H is a positive integer, H is a horizontal period, and d×H is a pulse width of first and second gate signals).
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