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公开(公告)号:US20160329391A1
公开(公告)日:2016-11-10
申请号:US15139228
申请日:2016-04-26
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor: MOO SOON KO , JUNG HWA KIM , MIN WOO WOO , WANG WOO LEE
IPC: H01L27/32
CPC classification number: H01L27/3262 , H01L27/1222 , H01L27/124 , H01L27/3216 , H01L27/3218 , H01L27/322 , H01L27/326 , H01L27/3276
Abstract: An organic light-emitting diode display is disclosed. In one aspect, a semiconductor layer is on a substrate, and the semiconductor layer is non-linear. A gate metal line is on the semiconductor layer, and an insulating layer covering the semiconductor layer and the gate metal line and having a plurality of contact holes connected to the semiconductor layer. A data metal line is on the insulating layer and electrically connected to the semiconductor layer via a selected one of the contact holes. An OLED is electrically connected to the gate metal line and the data metal line, and the semiconductor layer includes a narrow semiconductor layer having a first width and an expansion semiconductor layer formed adjacent to the selected contact hole and having a second width greater than the first width.
Abstract translation: 公开了一种有机发光二极管显示器。 在一个方面,半导体层在衬底上,半导体层是非线性的。 栅极金属线位于半导体层上,绝缘层覆盖半导体层和栅极金属线,并具有与半导体层连接的多个接触孔。 数据金属线位于绝缘层上,并通过选定的一个接触孔与半导体层电连接。 OLED与栅极金属线和数据金属线电连接,并且半导体层包括具有第一宽度的窄半导体层和邻近所选接触孔形成的第二宽度的第二宽度的第二宽度的半导体层。 宽度。
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公开(公告)号:US20190229160A1
公开(公告)日:2019-07-25
申请号:US16148436
申请日:2018-10-01
Applicant: SAMSUNG DISPLAY CO. LTD.
Inventor: JI SEON LEE , MOO SOON KO , YOUNG WOO PARK , SE WAN SON , JIN SUNG AN , MIN WOO WOO , JU WON YOON , WANG WOO LEE , JEONG SOO LEE , DEUK MYUNG JI
Abstract: A display device includes a substrate including a display area and a non-display area. First, second, and third insulating layers are sequentially disposed on the substrate. Pixels are disposed in the display area. Each of the pixels including a transistor and a light emitting element connected to the transistor. A data line is disposed in the display area. The data line is configured to supply a data signal to each of the plurality of pixels. A wiring portion is disposed in the non-display area. The wiring portion includes a connecting line connected to the data line and a fan-out line connected to the connecting line. A dummy pattern is disposed in the non-display area. The dummy pattern at least partially overlaps the wiring portion.
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公开(公告)号:US20240404895A1
公开(公告)日:2024-12-05
申请号:US18804531
申请日:2024-08-14
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor: MOO SOON KO , JEONG-SOO LEE , JUNG HWA KIM
IPC: H01L21/66 , G09G3/00 , G09G3/3233 , H01L27/12 , H01L29/786 , H10K59/12 , H10K59/88
Abstract: A display device is disclosed. In one aspect, the display device includes a display area configured to display an image, a peripheral area neighboring the display area, and at least one test element group (TEG) including a test thin film transistor (TFT) formed in the peripheral area and a plurality of test pads electrically connected to the test TFT. The display device also includes first to third dummy circuits separated from the test TFT, each of the first to third dummy circuits including a plurality of first dummy semiconductor layers and a plurality of first dummy gate electrodes overlapping at least a portion of the first dummy semiconductor layers in the depth dimension of the display device.
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公开(公告)号:US20210272860A1
公开(公告)日:2021-09-02
申请号:US17321980
申请日:2021-05-17
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor: MOO SOON KO , JEONG-SOO LEE , JUNG HWA KIM
IPC: H01L21/66 , H01L27/12 , G09G3/3233 , G09G3/00 , H01L29/786
Abstract: A display device is disclosed. In one aspect, the display device includes a display area configured to display an image, a peripheral area neighboring the display area, and at least one test element group (TEG) including a test thin film transistor (TFT) formed in the peripheral area and a plurality of test pads electrically connected to the test TFT. The display device also includes first to third dummy circuits separated from the test TFT, each of the first to third dummy circuits including a plurality of first dummy semiconductor layers and a plurality of first dummy gate electrodes overlapping at least a portion of the first dummy semiconductor layers in the depth dimension of the display device.
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公开(公告)号:US20210126071A1
公开(公告)日:2021-04-29
申请号:US17140484
申请日:2021-01-04
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor: JEONG-SOO LEE , MOO SOON KO , MIN WOO WOO , JU-WON YOON , DEUK MYUNG JI
IPC: H01L27/32 , H01L29/786 , G09G3/3258 , H01L27/12 , G09G3/3233
Abstract: A display device includes a plurality of pixels. Each pixel includes a first transistor including a first gate electrode, a first source region, and a first drain region, a second transistor connected to the first source region of the first transistor, a third transistor connected to the first gate electrode and the first drain region of the first transistor, a fifth transistor connected to the first source region of the first transistor, and a sixth transistor connected to the first drain region of the first transistor. The pixels include a first pixel and a second pixel disposed adjacent to each other. The first and second pixels share a fourth transistor connected to the third transistor of the first pixel and the third transistor of the second pixel, and share a seventh transistor connected to the sixth transistor of the first pixel and the sixth transistor of the second pixel.
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公开(公告)号:US20190181065A1
公开(公告)日:2019-06-13
申请号:US16277414
申请日:2019-02-15
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor: MOO SOON KO , JEONG-SOO LEE , JUNG HWA KIM
IPC: H01L21/66 , H01L27/12 , H01L29/786
Abstract: A display device is disclosed. In one aspect, the display device includes a display area configured to display an image, a peripheral area neighboring the display area, and at least one test element group (TEG) including a test thin film transistor (TFT) formed in the peripheral area and a plurality of test pads electrically connected to the test TFT. The display device also includes first to third dummy circuits separated from the test TFT, each of the first to third dummy circuits including a plurality of first dummy semiconductor layers and a plurality of first dummy gate electrodes overlapping at least a portion of the first dummy semiconductor layers in the depth dimension of the display device.
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