公开(公告)号：US20230110126A1

公开(公告)日：2023-04-13

申请号：US17804104

申请日：2022-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： JEONGHYUN LEE ,  DONGWOOK KIM ,  HYUNGLAK MA ,  JIYONG PARK ,  HWANPIL PARK

IPC: H01L23/498 ,  H01L25/16 ,  H01L23/00

Abstract: A semiconductor package includes a package substrate that includes a substrate base and a lower solder resist layer that covers a lower surface of the substrate base, where the lower solder resist layer includes a ponding recess that extends from a lower surface toward an upper surface of the lower solder resist layer, a semiconductor chip attached to an upper surface of the package substrate, an auxiliary chip attached to a lower surface of the package substrate adjacent to the ponding recess through a plurality of chip terminals, where the auxiliary chip includes a first side and a second side opposite to each other in a plane, and an underfill layer that fills a space between the package substrate and the auxiliary chip, surrounds the plurality of chip terminals, and fills the ponding recess.