公开(公告)号：US20230154866A1

公开(公告)日：2023-05-18

申请号：US17875639

申请日：2022-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Juyoun CHOI ,  Miyeon KIM ,  Jungil SON

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/14 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06589 ,  H01L2224/14517 ,  H01L2924/1205 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/3511

Abstract: A semiconductor package includes a package base substrate including a potential plate. An interposer is arranged on the package base substrate and comprises at least one interposer through electrode, at least one first connection bump, and at least one second connection bump. A first stacked chip unit is arranged on the interposer and comprises a first semiconductor chip and at least one second semiconductor chips arranged on the first semiconductor chip. At least one passive device unit is arranged on the package base substrate. The at least one passive device unit is spaced apart from the interposer in a horizontal direction parallel to an upper surface of the package base substrate. The at least one first connection bump is a dummy bump. The potential plate electrically connects the at least one first connection bump and a power terminal of the at least one passive device unit to each other.