公开(公告)号：US20210225867A1

公开(公告)日：2021-07-22

申请号：US17007141

申请日：2020-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WOOSUNG YANG ,  BYUNGJIN LEE ,  BUMKYU KANG ,  JOONSUNG LIM

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11526 ,  G11C7/18 ,  H01L23/522 ,  H01L23/00

Abstract: A memory device includes a lower structure and a plurality of upper structures stacked on the lower structure. The lower structure includes a peripheral circuit, and an upper bonding pad disposed on a top surface of the lower structure. Each of the plurality of upper structures includes a bit line, a through via, and a lower bonding pad disposed on a bottom surface of the upper structures and connected to the through via. Each of upper structures, other than an uppermost upper structure, further includes an upper bonding pad disposed on a top surface thereof and connected to the through via. The bit line includes a gap separating a first portion of the bit line from a second portion thereof in the horizontal direction, and the through via overlaps the gap of the bit line in a plan view.

公开(公告)号：US20220406814A1

公开(公告)日：2022-12-22

申请号：US17895182

申请日：2022-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WOOSUNG YANG ,  BYUNGJIN LEE ,  BUMKYU KANG ,  JOONSUNG LIM

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11519 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11526 ,  G11C7/18 ,  H01L23/522 ,  H01L27/11524

Abstract: A memory device includes a lower structure and a plurality of upper structures stacked on the lower structure. The lower structure includes a peripheral circuit, and an upper bonding pad disposed on a top surface of the lower structure. Each of the plurality of upper structures includes a bit line, a through via, and a lower bonding pad disposed on a bottom surface of the upper structures and connected to the through via. Each of upper structures, other than an uppermost upper structure, further includes an upper bonding pad disposed on a top surface thereof and connected to the through via. The bit line includes a gap separating a first portion of the bit line from a second portion thereof in the horizontal direction, and the through via overlaps the gap of the bit line in a plan view.

公开(公告)号：US20210225871A1

公开(公告)日：2021-07-22

申请号：US17113456

申请日：2020-12-07

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： DONG-SIK LEE ,  BYUNGJIN LEE ,  SUNG-MIN HWANG

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11526

Abstract: A three-dimensional semiconductor memory device includes a substrate including cell and connection regions. An electrode structure is disposed on the substrate, the electrode structure having a staircase structure on the connection region. A first vertical channel structure and a first dummy structure at least partially penetrate the electrode structure on the cell region and the connection region, respectively. Bottoms of expanded portions of the first vertical channel structure and the first dummy structure are located at first and second levels, respectively. The second level is higher than the first level.

公开(公告)号：US20200373324A1

公开(公告)日：2020-11-26

申请号：US16773084

申请日：2020-01-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： BYUNGJIN LEE ,  Dong-sik Lee ,  Joon-Sung Lim

IPC: H01L27/11582 ,  H01L27/11565

Abstract: A semiconductor device is provided. The semiconductor device includes a stack structure that includes a plurality of dielectric layers spaced apart from each other on a substrate, a plurality of electrodes interposed between the plurality of dielectric layers, and a plurality of stopper layers interposed between the plurality of dielectric layers; and a vertical channel structure that penetrates the stack structure. Each of the plurality of electrodes and the plurality of stopper layers is disposed in a corresponding empty space interposed between the plurality of dielectric layers, the plurality of stopper layers includes a first stopper layer and a second stopper layer that is interposed between the first stopper layer and the substrate, and at least one of the plurality of electrodes is interposed between the first stopper layer and the second stopper layer.