公开(公告)号：US09711505B2

公开(公告)日：2017-07-18

申请号：US15094282

申请日：2016-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoung-Hak Hong ,  Bon-Woong Koo ,  Sung-Il Park ,  Kyu-Baik Chang ,  Keun-Hwi Cho ,  Dae-Won Ha

IPC: H01L23/52 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L29/4238 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a gate structure on a substrate. The gate structure includes a first gate insulation pattern, a conductive pattern for controlling a threshold voltage, a first gate electrode and a first mask sequentially stacked. A dummy gate structure is spaced apart from the gate electrode. The dummy gate structure includes a first stressor pattern including titanium oxide. Source/drain regions are adjacent to the gate structure. The source/drain regions are doped with p-type impurities. The first stressor pattern may apply a stress onto the channel region of a transistor, and consequently the transistor having good electrical characteristics may be obtained.