公开(公告)号：US10249757B2

公开(公告)日：2019-04-02

申请号：US15386901

申请日：2016-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bong Cheol Kim ,  Hyung Suk Lee ,  Eun Shoo Han

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/165 ,  H01L29/10

Abstract: A substrate includes a pattern forming region and a peripheral region. A first strain relaxed buffer layer is disposed on the pattern forming region of the substrate. A second strain relaxed buffer layer is disposed on the peripheral region of the substrate. A first insulating film pattern is disposed on the substrate. At least a portion of the first insulating film pattern is disposed within the first strain relaxed buffer layer. An upper surface of the first insulating film pattern is covered with the first strain relaxed buffer layer. A second insulating film pattern is disposed on the substrate. At least a portion of the second insulating film pattern is disposed within the second strain relaxed buffer layer. An upper surface of the second insulating film pattern is covered with the second strain relaxed buffer layer. A gate electrode is disposed on the first strain relaxed buffer layer.