公开(公告)号：US20240256724A1

公开(公告)日：2024-08-01

申请号：US18424345

申请日：2024-01-26

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Gyuduck BAE ,  Pilsung Koh ,  Sangsu Kim ,  Kyuman Yeon ,  Soyeon Lee ,  Bora Jeong ,  Boseok Hong ,  Jisan Kwak ,  Haegeun Park ,  Yonghwan Baek ,  Chulho Song ,  Seungyong Lee

IPC分类号： G06F30/13 ,  G06F111/20

CPC分类号： G06F30/13 ,  G06F2111/20

摘要： A method of determining a facility layout of a semiconductor factory including a main floor including processing zones, a clean sub-FAB (CSF) floor under the main floor, and a facility sub-FAB (FSF) floor under the CSF floor includes receiving data related to main facilities to be placed on the main floor, CSF subsidiary facilities to be placed on the CSF floor, and FSF subsidiary facilities to be placed on the FSF floor, and determining the facility layout including a layout of the main facilities for the main floor, a layout of the CSF subsidiary facilities for the CSF floor, and a layout of the FSF subsidiary facilities for the FSF floor.