公开(公告)号：US11849570B2

公开(公告)日：2023-12-19

申请号：US17348912

申请日：2021-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byeong Ju Bae ,  Seung-Heon Lee ,  Ik Soo Kim ,  Byoung Deog Choi

IPC: H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/84 ,  H10B63/24 ,  H10N70/011 ,  H10N70/231

Abstract: A semiconductor memory device and associated methods, the device including first and second lower conductive lines extending in a first direction; a first middle conductive line on the first and second lower conductive lines and extending in a second direction; first and second memory cells between the first and second lower conductive lines and the first middle conductive line; an air gap support layer between the first and second memory cells; and a first air gap between the first and second memory cells and under the air gap support layer, wherein an upper surface of the air gap support layer lies in a same plane as the first and second memory cells, the first and second memory cells include first and second OTS layers and first and second phase-change layers, and the first air gap overlaps the first and second phase-change layers.