公开(公告)号：US11810852B2

公开(公告)日：2023-11-07

申请号：US17707267

申请日：2022-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daae Huh ,  Dongyeop Kim

IPC: H01L23/522 ,  H01L23/64 ,  H01L25/18 ,  H05K1/16

CPC classification number: H01L23/5223

Abstract: A substrate for semiconductor module includes a plurality of insulating layers sequentially stacked on one another, N signal lines transmitting N signals respectively, the N signal lines having N vias that at least partially penetrate through the plurality of insulating layers and are arranged in an N-sided polygon shape in a plan view, and a capacitor element configured to provide capacitive coupling between the N signal lines, the capacitor element having a first coupling element that provides capacitive coupling between first and second vias adjacent to each other among the N vias and a second coupling element that provides capacitive coupling between third and fourth vias that are not adjacent to each other among the N vias.